Optimized process for fabrication of free-standing silicon nanophotonic devices

Optimizing epsilon-near-zero based plasmon assisted modulators through surface-to-volume ratio

Plasmonic-based integrated nanophotonic modulators, despite their promising features, have one key limiting factor of large insertion loss (IL), which limits their practical potential. To combat this, we utilize a plasmon-assisted approach through the lens of surface-to-volume ratio to realize a 4-slot based EAM with an extinction ratio (ER) of 2.62 dB/µm and insertion loss (IL) of 0.3 dB/µm operating at ∼1 GHz and a single slot design with ER of 1.4 dB/µm and IL of 0.25 dB/µm operating at ∼20 GHz, achieved by replacing the traditional metal contact with heavily doped indium tin oxide (ITO). Furthermore, our analysis imposes realistic fabrication constraints, and material properties, and illustrates trade-offs in the performance that must be carefully optimized for a given scenario.

Array of Graphene Variable Capacitors on 100 mm Silicon Wafers for Vibration-Based Applications

Highly flexible, electrically conductive freestanding graphene membranes hold great promise for vibration-based applications. This study focuses on their integration into mainstream semiconductor manufacturing methods. We designed a two-mask lithography process that creates an array of freestanding graphene-based variable capacitors on 100 mm silicon wafers. The first mask forms long trenches terminated by square wells featuring cone-shaped tips at their centers. The second mask fabricates metal traces from each tip to its contact pad along the trench and a second contact pad opposite the square well. A graphene membrane is then suspended over the square well to form a variable capacitor. The same capacitor structures were also built on 5 mm by 5 mm bare dies containing an integrated circuit underneath. We used atomic force microscopy, optical microscopy, and capacitance measurements in time to characterize the samples.