The Study of Electrical Properties for Multilayer La2O3/Al2O3 Dielectric Stacks and LaAlO3 Dielectric Film Deposited by ALD

Border Trap Extraction with Capacitance- Equivalent Thickness to Reflect the Quantum Mechanical Effect on Atomic Layer Deposition High-k/In0.53Ga0.47As on 300-mm Si Substrate

This study presents a model to calculate the border trap density (N_bt) of atomic layer deposition high-k onto In_0.53Ga_0.47As on a 300-mm (001) Si substrate. This model considers the quantum confinement effect and band nonparabolicity. Capacitance-equivalent thickness (CET) was used to reflect the distance of the charge centroid from the oxide-semiconductor interface. The border trap values based on CET were found to be approximately 65% lower than the extracted values based on physical thickness in the In_0.53Ga_0.47As material. In an investigation of two different post-metal annealing effects on border traps, the border trap was more effectively passivated by N₂-based forming gas annealing (FGA) compared with rapid thermal annealing (RTA), whereas a lower interface state density was observed in RTA-annealed samples compared with FGA-annealed samples. N_bt extraction at different bias voltages demonstrated that the applied frequencies travel deep into the oxide and interact with more traps as more the Fermi level passes the conduction band, thus creating tunneling with the carriers.