Numerical Verification of Gallium Nitride Thin-Film Growth in a Large MOCVD Reactor

A Modeling and Experimental Study on the Growth of VCSEL Materials Using an 8 × 6 Inch Planetary MOCVD Reactor

VCSEL (vertical cavity surface emitting laser) is a promising optoelectronic device, but its high manufacturing cost limits its scope of applications. Growing on larger size wafers is an effective way to reduce the cost. However, the growth rate uniformity needs to be optimized to ensure the uniformity of the devices’ performance over the wafers. This paper investigates the factors which influence the growth rate uniformity using an 8 × 6 inch planetary reactor through experiments and simulations. At a carrier gas flow rate of 37 slm, an AsH3 flow rate of 600 sccm, an AsH3 flow rate ratio of 100:500, and a ceiling temperature of 175 °C, the growth rate uniformity of the AlGaAs layer with a relative standard deviation of 0.16%, 1σ, was obtained over the 6-inch wafers. The uniformity of the DBR stop band center and VCSEL quantum well wavelength with standard deviations of 0.142% and 0.023%, 1σ, were received over the 6-inch wafers, respectively. Based on the optimized results, 99.95% of VCSEL devices with wavelengths of 940 ± 5 nm were realized over the 6-inch wafers.

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

During the formation of Ge fin structures on a silicon-on-insulator (SOI) substrate, we found that the dry etching process must be carefully controlled. Otherwise, it may lead to Ge over-etching or the formation of an undesirable Ge fin profile. If the etching process is not well controlled, the top Ge/SOI structure is etched away, and only the Si fin layer remains. In this case, the device exhibits abnormal characteristics. The etching process is emerging as a critical step in device scaling and packaging and affects attempts to increase the packing density and improve device performance. Therefore, it is suggested that optimization of operating the plasma reactor be performed through simulations, in order to not only adjust the process parameters used but also to modify the hardware employed. We are going to develop Ge junction-less devices by employing updated fabrication parameters. Besides, we want to eliminate misfit dislocations at the interface or to reduce threading dislocations by applying cyclic thermal annealing process to meet the goal of obtaining suspended structure of epitaxial Ge layers with high quality.