Approaching Retinal Ganglion Cell Modeling and FPGA Implementation for Robotics

A spiking and adapting tactile sensor for neuromorphic applications

The ongoing research on and development of increasingly intelligent artificial systems propels the need for bio inspired pressure sensitive spiking circuits. Here we present an adapting and spiking tactile sensor, based on a neuronal model and a piezoelectric field-effect transistor (PiezoFET). The piezoelectric sensor device consists of a metal-oxide semiconductor field-effect transistor comprising a piezoelectric aluminium-scandium-nitride (AlxSc1-xN) layer inside of the gate stack. The so augmented device is sensitive to mechanical stress. In combination with an analogue circuit, this sensor unit is capable of encoding the mechanical quantity into a series of spikes with an ongoing adaptation of the output frequency. This allows for a broad application in the context of robotic and neuromorphic systems, since it enables said systems to receive information from the surrounding environment and provide encoded spike trains for neuromorphic hardware. We present numerical and experimental results on this spiking and adapting tactile sensor.

Event-Based Gesture Recognition through a Hierarchy of Time-Surfaces for FPGA

Neuromorphic vision sensors detect changes in luminosity taking inspiration from mammalian retina and providing a stream of events with high temporal resolution, also known as Dynamic Vision Sensors (DVS). This continuous stream of events can be used to extract spatio-temporal patterns from a scene. A time-surface represents a spatio-temporal context for a given spatial radius around an incoming event from a sensor at a specific time history. Time-surfaces can be organized in a hierarchical way to extract features from input events using the Hierarchy Of Time-Surfaces algorithm, hereinafter HOTS. HOTS can be organized in consecutive layers to extract combination of features in a similar way as some deep-learning algorithms do. This work introduces a novel FPGA architecture for accelerating HOTS network. This architecture is mainly based on block-RAM memory and the non-restoring square root algorithm, requiring basic components and enabling it for low-power low-latency embedded applications. The presented architecture has been tested on a Zynq 7100 platform at 100 MHz. The results show that the latencies are in the range of 1 μ s to 6.7 μ s, requiring a maximum dynamic power consumption of 77 mW. This system was tested with a gesture recognition dataset, obtaining an accuracy loss for 16-bit precision of only 1.2% with respect to the original software HOTS.

Field Programmable Gate Array Applications—A Scientometric Review

Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.