In-Memory Computing with Resistive Memory Circuits: Status and Outlook

Capacitive and Inductive Characteristics of Volatile Perovskite Resistive Switching Devices with Analog Memory

With the increasing demands and complexity of the neuromorphic computing schemes utilizing highly efficient analog resistive switching devices, understanding the apparent capacitive and inductive effects in device operation is of paramount importance. Here, we present a systematic array of characterization methods that unravel two distinct voltage-dependent regimes demonstrating the complex interplay between the dynamic capacitive and inductive effects in volatile perovskite-based memristors: (1) a low voltage capacitance-dominant and (2) an inductance-dominant regime evidenced by the highly correlated hysteresis type with nonzero crossing, the impedance responses, and the transient current characteristics. These dynamic capacitance- and inductance-dominant regimes provide fundamental insight into the resistive switching of memristors governing the synaptic depression and potentiation functions, respectively. More importantly, the pulse width-dependent and long-term transient current measurements further demonstrate a dynamic transition from a fast capacitive to a slow inductive response, allowing for the tailored stimulus programming of memristor devices to mimic synaptic functionality.

Ultra-fast switching memristors based on two-dimensional materials

The ability to scale two-dimensional (2D) material thickness down to a single monolayer presents a promising opportunity to realize high-speed energy-efficient memristors. Here, we report an ultra-fast memristor fabricated using atomically thin sheets of 2D hexagonal Boron Nitride, exhibiting the shortest observed switching speed (120 ps) among 2D memristors and low switching energy (2pJ). Furthermore, we study the switching dynamics of these memristors using ultra-short (120ps-3ns) voltage pulses, a frequency range that is highly relevant in the context of modern complementary metal oxide semiconductor (CMOS) circuits. We employ statistical analysis of transient characteristics to gain insights into the memristor switching mechanism. Cycling endurance data confirms the ultra-fast switching capability of these memristors, making them attractive for next generation computing, storage, and Radio-Frequency (RF) circuit applications.

A Star Network of Bipolar Memristive Devices Enables Sensing and Temporal Computing

Temporal (race) computing schemes rely on temporal memories, where information is represented with the timing of signal edges. Standard digital circuit techniques can be used to capture the relative timing characteristics of signal edges. However, the properties of emerging device technologies could be particularly exploited for more efficient circuit implementations. Specifically, the collective dynamics of networks of memristive devices could be leveraged to facilitate time-domain computations in emerging memristive memories. To this end, this work studies the star interconnect configuration of bipolar memristive devices. Through circuit simulations using a behavioral model of voltage-controlled bipolar memristive devices, we demonstrated the suitability of such circuits in two different contexts, namely sensing and "rank-order" coding. We particularly analyzed the conditions that the employed memristive devices should meet to guarantee the expected operation of the circuit and the possible effects of device variability in the storage and the reproduction of the information in arriving signal edges. The simulation results in LTSpice validate the correct operation and confirm the promising application prospects of such simple circuit structures, which, we show, natively exist in the crossbar geometry. Therefore, the star interconnect configuration could be considered for temporal computations inside resistive memory (ReRAM) arrays.

A bi-functional three-terminal memristor applicable as an artificial synapse and neuron

Due to their significant resemblance to the biological brain, spiking neural networks (SNNs) show promise in handling spatiotemporal information with high time and energy efficiency. Two-terminal memristors have the capability to achieve both synaptic and neuronal functions; however, such memristors face asynchronous programming/reading operation issues. Here, a three-terminal memristor (3TM) based on oxygen ion migration is developed to function as both a synapse and a neuron. We demonstrate short-term plasticity such as pair-pulse facilitation and high-pass dynamic filtering in our devices. Additionally, a 'learning-forgetting-relearning' behavior is successfully mimicked, with lower power required for the relearning process than the first learning. Furthermore, by leveraging the short-term dynamics, the leaky-integrate-and-fire neuronal model is emulated by the 3TM without adopting an external capacitor to obtain the leakage property. The proposed bi-functional 3TM offers more process compatibility for integrating synaptic and neuronal components in the hardware implementation of an SNN.

Highly Reliable Textile-Type Memristor by Designing Aligned Nanochannels

Information-processing devices are the core components of modern electronics. Integrating them into textiles is the indispensable demand for electronic textiles to form close-loop functional systems. Memristors with crossbar configuration are regarded as promising building blocks to design woven information-processing devices that seamlessly unify with textiles. However, the memristors always suffer from severe temporal and spatial variations due to the random growth of conductive filaments during filamentary switching processes. Here, inspired by the ion nanochannels across synaptic membranes, a highly reliable textile-type memristor made of Pt/CuZnS memristive fiber with aligned nanochannels, showing small set voltage variation (<5.6%) under ultralow set voltage (≈0.089 V), high on/off ratio (≈106 ), and low power consumption (0.1 nW), is reported. Experimental evidence indicate that nanochannels with abundant active S defects can anchor silver ions and confine their migrations to form orderly and efficient conductive filaments. Such memristive performances enable the resultant textile-type memristor array to have high device-to-device uniformity and process complex physiological data like brainwave signals with high recognition accuracy (95%). The textile-type memristor arrays are mechanically durable to withstand hundreds of bending and sliding deformations, and seamlessly unified with sensing, power-supplying, and displaying textiles/fibers to form all-textile integrated electronic systems for new generation human-machine interactions.

Reproducible Non-Volatile Multi-State Storage and Emulation of Synaptic Plasticity Based on a Copper-Nanoparticle-Embedded HfOx/ZnO Bilayer with Ultralow-Switching Current and Ideal Data Retention

The multilevel properties of a memristor are significant for applications in non-volatile multi-state storage and electronic synapses. However, the reproducibility and stability of the intermediate resistance states are still challenging. A stacked HfOx/ZnO bilayer embedded with copper nanoparticles was thus proposed to investigate its multilevel properties and to emulate synaptic plasticity. The proposed memristor operated at the microampere level, which was ascribed to the barrier at the HfOx/ZnO interface suppressing the operational current. Compared with the stacked HfOx/ZnO bilayer without nanoparticles, the proposed memristor had a larger ON/OFF resistance ratio (~330), smaller operational voltages (absolute value < 3.5 V) and improved cycle-to-cycle reproducibility. The proposed memristor also exhibited four reproducible non-volatile resistance states, which were stable and well retained for at least ~1 year at 85 °C (or ~10 years at 70 °C), while for the HfOx/ZnO bilayer without copper nanoparticles, the minimum retention time of its multiple resistance states was ~9 days at 85 °C (or ~67 days at 70 °C). Additionally, the proposed memristor was capable of implementing short-term and long-term synaptic plasticities.

Medium-Temperature-Oxidized GeOx Resistive-Switching Random-Access Memory and Its Applicability in Processing-in-Memory Computing

Processing-in-memory (PIM) is emerging as a new computing paradigm to replace the existing von Neumann computer architecture for data-intensive processing. For the higher end-user mobility, low-power operation capability is more increasingly required and components need to be renovated to make a way out of the conventional software-driven artificial intelligence. In this work, we investigate the hardware performances of PIM architecture that can be presumably constructed by resistive-switching random-access memory (ReRAM) synapse fabricated with a relatively larger thermal budget in the full Si processing compatibility. By introducing a medium-temperature oxidation in which the sputtered Ge atoms are oxidized at a relatively higher temperature compared with the ReRAM devices fabricated by physical vapor deposition at room temperature, higher device reliability has been acquired. Based on the empirically obtained device parameters, a PIM architecture has been conceived and a system-level evaluations have been performed in this work. Considerations include the cycle-to-cycle variation in the GeO_x ReRAM synapse, analog-to-digital converter resolution, synaptic array size, and interconnect latency for the system-level evaluation with the Canadian Institute for Advance Research-10 dataset. A fully Si processing-compatible and robust ReRAM synapse and its applicability for PIM are demonstrated.

High-Density Solid-State Memory Devices and Technologies

The relevance of solid-state memories in the world of electronics is on the constant rise [...]

Retinomorphic optoelectronic devices for intelligent machine vision

Biological visual system can efficiently handle optical information within the retina and visual cortex of the brain, which suggests an alternative approach for the upgrading of the current low-intelligence, large energy consumption, and complex circuitry of the artificial vision system for high-performance edge computing applications. In recent years, retinomorphic machine vision based on the integration of optoelectronic image sensors and processors has been regarded as a promising candidate to improve this phenomenon. This novel intelligent machine vision technology can perform information preprocessing near or even within the sensor in the front end, thereby reducing the transmission of redundant raw data and improving the efficiency of the back-end processor for high-level computing tasks. In this contribution, we try to present a comprehensive review on the recent progress achieved in this emergent field.

Multi-Level Resistive Switching of Pt/HfO2/TaN Memory Device

This work characterizes resistive switching and neuromorphic simulation of Pt/HfO2/TaN stack as an artificial synaptic device. A stable bipolar resistive switching operation is performed by repetitive DC sweep cycles. Furthermore, endurance (DC 100 cycles) and retention (5000 s) are demonstrated for reliable resistive operation. Low-resistance and high-resistance states follow the Ohmic conduction and Poole–Frenkel emission, respectively, which is verified through the fitting process. For practical operation, the set and reset processes are performed through pulses. Further, potentiation and depression are demonstrated for neuromorphic application. Finally, neuromorphic system simulation is performed through a neural network for pattern recognition accuracy of the Fashion Modified National Institute of Standards and Technology dataset.

Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements

The machine learning and convolutional neural network (CNN)-based intelligent artificial accelerator needs significant parallel data processing from the cache memory. The separate read port is mostly used to design built-in computational memory (CRAM) to reduce the data processing bottleneck. This memory uses multi-port reading and writing operations, which reduces stability and reliability. In this paper, we proposed a self-adaptive 12T SRAM cell to increase the read stability for multi-port operation. The self-adaptive technique increases stability and reliability. We increased the read stability by refreshing the storing node in the read mode of operation. The proposed technique also prevents the bit-interleaving problem. Further, we offered a butterfly-inspired SRAM bank to increase the performance and reduce the power dissipation. The proposed SRAM saves 12% more total power than the state-of-the-art 12T SRAM cell-based SRAM. We improve the write performance by 28.15% compared with the state-of-the-art 12T SRAM design. The total area overhead of the proposed architecture compared to the conventional 6T SRAM cell-based SRAM is only 1.9 times larger than the 6T SRAM cell.

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing

Logic-in-memory (LIM) circuits based on the material implication logic (IMPLY) and resistive random access memory (RRAM) technologies are a candidate solution for the development of ultra-low power non-von Neumann computing architectures. Such architectures could enable the energy-efficient implementation of hardware accelerators for novel edge computing paradigms such as binarized neural networks (BNNs) which rely on the execution of logic operations. In this work, we present the multi-input IMPLY operation implemented on a recently developed smart IMPLY architecture, SIMPLY, which improves the circuit reliability, reduces energy consumption, and breaks the strict design trade-offs of conventional architectures. We show that the generalization of the typical logic schemes used in LIM circuits to multi-input operations strongly reduces the execution time of complex functions needed for BNNs inference tasks (e.g., the 1-bit Full Addition, XNOR, Popcount). The performance of four different RRAM technologies is compared using circuit simulations leveraging a physics-based RRAM compact model. The proposed solution approaches the performance of its CMOS equivalent while bypassing the von Neumann bottleneck, which gives a huge improvement in bit error rate (by a factor of at least 10⁸) and energy-delay product (projected up to a factor of 10¹⁰).

Energy-Efficient Non-Von Neumann Computing Architecture Supporting Multiple Computing Paradigms for Logic and Binarized Neural Networks

Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized neural networks (BNNs) inference. However, operation-specific hardware accelerators can result in better performance for a particular task, such as the analog computation of the multiply and accumulate operation for BNN inference, but lack reconfigurability. Nonetheless, a solution providing the flexibility of SIMPLY while also achieving the high performance of BNN-specific analog hardware accelerators is missing. In this work, we propose a novel in-memory architecture based on 1T1R crossbar arrays, which enables the coexistence on the same crossbar array of both SIMPLY computing paradigm and the analog acceleration of the multiply and accumulate operation for BNN inference. We also highlight the main design tradeoffs and opportunities enabled by different emerging non-volatile memory technologies. Finally, by using a physics-based Resistive Random Access Memory (RRAM) compact model calibrated on data from the literature, we show that the proposed architecture improves the energy delay product by >103 times when performing a BNN inference task with respect to a SIMPLY implementation.