A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

A Low-Power, Fast-Transient Output-Capacitorless LDO with Transient Enhancement Unit and Current Booster

With the wide application of advanced portable devices, output-capacitorless low dropout regulators (OCL-LDO) are receiving increasing attention. This paper presents a low quiescent current OCL-LDO with fast transient response. A transient enhancement unit (TEU) is proposed as the output voltage-spike detection circuit. It enhances the transient response by improving the slew-rate at the gate of the power transistor. In addition, a current booster (CB), which consists of a current subtractor and a non-linear current mirror, is designed to improve the slew-rate further. The current subtractor increases the transconductances of the differential-input transistors to obtain a large slewing current, while the non-linear current mirror further boosts the current with no extra quiescent current consumption. The simulated results show that the proposed OCL-LDO is capable of supplying 100 mA load current while consuming 10.3 μA quiescent current. It regulates the output at 1 V from a supply voltage ranging from 1.2 to 1.8 V. When the load current is stepped from 1 mA to 100 mA in 100 ns, the OCL-LDO has attained a settling time of 190 ns, and the output voltage undershoot and overshoot are controlled under 110 mV.

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.