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Lee C, Rahimifard L, Choi J, Park JI, Lee C, Kumar D, Shukla P, Lee SM, Trivedi AR, Yoo H, Im SG. Highly parallel and ultra-low-power probabilistic reasoning with programmable gaussian-like memory transistors. Nat Commun 2024; 15:2439. [PMID: 38499561 PMCID: PMC10948914 DOI: 10.1038/s41467-024-46681-2] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Key Words] [Grants] [Track Full Text] [Journal Information] [Subscribe] [Scholar Register] [Received: 10/18/2023] [Accepted: 03/06/2024] [Indexed: 03/20/2024] Open
Abstract
Probabilistic inference in data-driven models is promising for predicting outputs and associated confidence levels, alleviating risks arising from overconfidence. However, implementing complex computations with minimal devices still remains challenging. Here, utilizing a heterojunction of p- and n-type semiconductors coupled with separate floating-gate configuration, a Gaussian-like memory transistor is proposed, where a programmable Gaussian-like current-voltage response is achieved within a single device. A separate floating-gate structure allows for exquisite control of the Gaussian-like current output to a significant extent through simple programming, with an over 10000 s retention performance and mechanical flexibility. This enables physical evaluation of complex distribution functions with the simplified circuit design and higher parallelism. Successful implementation for localization and obstacle avoidance tasks is demonstrated using Gaussian-like curves produced from Gaussian-like memory transistor. With its ultralow-power consumption, simplified design, and programmable Gaussian-like outputs, our 3-terminal Gaussian-like memory transistor holds potential as a hardware platform for probabilistic inference computing.
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Affiliation(s)
- Changhyeon Lee
- Department of Chemical and Biomolecular Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Korea
| | - Leila Rahimifard
- Department of Electrical and Computer Engineering, University of Illinois at Chicago, Chicago, IL, 60607, USA
| | - Junhwan Choi
- Department of Chemical Engineering, Dankook University, 152 Jukjeon-ro, Suji-gu, Yongin, Gyeonggi-do, 16890, Korea
| | - Jeong-Ik Park
- Department of Chemical and Biomolecular Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Korea
| | - Chungryeol Lee
- Department of Chemical and Biomolecular Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Korea
| | - Divake Kumar
- Department of Electrical and Computer Engineering, University of Illinois at Chicago, Chicago, IL, 60607, USA
| | - Priyesh Shukla
- Department of Electrical and Computer Engineering, University of Illinois at Chicago, Chicago, IL, 60607, USA
| | - Seung Min Lee
- Department of Chemical and Biomolecular Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Korea
| | - Amit Ranjan Trivedi
- Department of Electrical and Computer Engineering, University of Illinois at Chicago, Chicago, IL, 60607, USA.
| | - Hocheon Yoo
- Department of Electronic Engineering, Gachon University, 1342 Seongnam-daero, Sujeong-gu, Seongnam, Gyeonggi-do, 13120, Korea.
| | - Sung Gap Im
- Department of Chemical and Biomolecular Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Korea.
- KAIST Institute for NanoCentury (KINC), Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Korea.
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Alimisis V, Gennis G, Gourdouparis M, Dimas C, Sotiriadis PP. A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application. SENSORS (BASEL, SWITZERLAND) 2023; 23:3978. [PMID: 37112319 PMCID: PMC10145287 DOI: 10.3390/s23083978] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Figures] [Subscribe] [Scholar Register] [Received: 03/16/2023] [Revised: 04/08/2023] [Accepted: 04/11/2023] [Indexed: 06/19/2023]
Abstract
A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power and area efficiency. Nonetheless, using subthreshold region techniques and a low power supply voltage (at only 0.6 V), the overall power consumption is 72 μW. The classifier consists of two main components, the learning and the classification blocks, both of which are based on the mathematical equations of the hardware-friendly algorithm. Based on a real-world dataset, the proposed classifier achieves only 1.4% less average accuracy than a software-based implementation of the same model. Both design procedure and all post-layout simulations are conducted in the Cadence IC Suite, in a TSMC 90 nm CMOS process.
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Nanopower Integrated Gaussian Mixture Model Classifier for Epileptic Seizure Prediction. Bioengineering (Basel) 2022; 9:bioengineering9040160. [PMID: 35447720 PMCID: PMC9028754 DOI: 10.3390/bioengineering9040160] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 03/22/2022] [Revised: 04/01/2022] [Accepted: 04/04/2022] [Indexed: 11/17/2022] Open
Abstract
This paper presents a new analog front-end classification system that serves as a wake-up engine for digital back-ends, targeting embedded devices for epileptic seizure prediction. Predicting epileptic seizures is of major importance for the patient’s quality of life as they can lead to paralyzation or even prove fatal. Existing solutions rely on power hungry embedded digital inference engines that typically consume several μW or even mW. To increase the embedded device’s autonomy, a new approach is presented combining an analog feature extractor with an analog Gaussian mixture model-based binary classifier. The proposed classification system provides an initial, power-efficient prediction with high sensitivity to switch on the digital engine for the accurate evaluation. The classifier’s circuit is chip-area efficient, operating with minimal power consumption (180 nW) at low supply voltage (0.6 V), allowing long-term continuous operation. Based on a real-world dataset, the proposed system achieves 100% sensitivity to guarantee that all seizures are predicted and good specificity (69%), resulting in significant power reduction of the digital engine and therefore the total system. The proposed classifier was designed and simulated in a TSMC 90 nm CMOS process, using the Cadence IC suite.
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