Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

An Effective Clustering Algorithm for the Low-Quality Image of Integrated Circuits via High-Frequency Texture Components Extraction

Verification is one of the core steps in integrated circuits (ICs) manufacturing due to the multifarious defects and malicious hardware Trojans (HTs). In most cases, the effectiveness of the detection relies on the quality of the sample images of ICs. However, the high-precision and noiseless images are hard to capture due to the mechanical precision, manual error and environmental interference. In this paper, an effective approach for processing the low-quality image data of ICs is proposed. Our approach can successfully categorize the partial pictures of multiple objected ICs with low resolution and various noise. The proposed approach extracts the high-frequency texture components (HFTC) of the images and constructs a graph with the correlationship among features. Subsequently, the spectral clustering is conducted for obtaining the final cluster indicators. The low-quality images of ICs can be successfully categorized by the proposed approach, which will provide a data foundation for the following verification tasks. In order to evaluate the effectiveness of the proposed approach, several experiments are conducted in the simulated datasets, which are generated by corrupting the real-world data in different conditions. The clustering results reveal that our approach can achieve the best performance with good stability compared to the baselines.

Approximate Computing Circuits for Embedded Tactile Data Processing

In this paper, we demonstrate the feasibility and efficiency of approximate computing techniques (ACTs) in the embedded Support Vector Machine (SVM) tensorial kernel circuit implementation in tactile sensing systems. Improving the performance of the embedded SVM in terms of power, area, and delay can be achieved by implementing approximate multipliers in the SVD. Singular Value Decomposition (SVD) is the main computational bottleneck of the tensorial kernel approach; since digital multipliers are extensively used in SVD implementation, we aim to optimize the implementation of the multiplier circuit. We present the implementation of the approximate SVD circuit based on the Approximate Baugh-Wooley (Approx-BW) multiplier. The approximate SVD achieves an energy consumption reduction of up to 16% at the cost of a Mean Relative Error decrease (MRE) of less than 5%. We assess the impact of the approximate SVD on the accuracy of the classification; showing that approximate SVD increases the Error rate (Err) within a range of one to eight percent. Besides, we propose a hybrid evaluation test approach that consists of implementing three different approximate SVD circuits having different numbers of approximated Least Significant Bits (LSBs). The results show that energy consumption is reduced by more than five percent with the same accuracy loss.