Neural Spike Digital Detector on FPGA

Noise Power Minimization in CMOS Brain-Chip Interfaces

This paper presents specific noise minimization strategies to be adopted in silicon–cell interfaces. For this objective, a complete and general model for the analog processing of the signal coming from cell–silicon junctions is presented. This model will then be described at the level of the single stages and of the fundamental parameters that characterize them (bandwidth, gain and noise). Thanks to a few design equations, it will therefore be possible to simulate the behavior of a time-division multiplexed acquisition channel, including the most relevant parameters for signal processing, such as amplification (or power of the analog signal) and noise. This model has the undoubted advantage of being particularly simple to simulate and implement, while maintaining high accuracy in estimating the signal quality (i.e., the signal-to-noise ratio, SNR). Thanks to the simulation results of the model, it will be possible to set an optimal operating point for the front-end to minimize the artifacts introduced by the time-division multiplexing (TDM) scheme and to maximize the SNR at the a-to-d converter input. The proposed results provide an SNR of 12 dB at 10 µV_RMS of noise power and 50 µV_RMS of signal power (both evaluated at input of the analog front-end, AFE). This is particularly relevant for cell–silicon junctions because it demonstrates that it is possible to detect weak extracellular events (of the order of few µV_RMS) without necessarily increasing the total amplification of the front-end (and, therefore, as a first approximation, the dissipated electrical power), while adopting a specific gain distribution through the acquisition chain.

SpikeOnChip : A Custom Embedded Platform for Neuronal Activity Recording and Analysis

In this paper we present SpikeOnChip, a custom embedded platform for neuronal activity recording and online analysis. The SpikeOnChip platform was developed in the context of automated drug testing and toxicology assessments on neural tissue made from human induced pluripotent stem cells. The system was developed with the following goals: to be small, autonomous and low power, to handle micro-electrode arrays with up to 256 electrodes, to reduce the amount of data generated from the recording, to be able to do computation during acquisition, and to be customizable. This led to the choice of a Field Programmable Gate Array System-On-Chip platform. This paper focuses on the embedded system for acquisition and processing with key features being the ability to record electrophysiological signals from multiple electrodes, detect biological activity on all channels online for recording, and do frequency domain spectral energy analysis online on all channels during acquisition. Development methodologies are also presented. The platform is finally illustrated in a concrete experiment with bicuculline being administered to grown human neural tissue through microfluidics, resulting in measurable effects in the spike recordings and activity. The presented platform provides a valuable new experimental instrument that can be further extended thanks to the programmable hardware and software.

Evaluation of In Vivo Spike Detection Algorithms for Implantable MTA Brain—Silicon Interfaces

This work presents a comparison between different neural spike algorithms to find the optimum for in vivo implanted EOSFET (electrolyte–oxide-semiconductor field effect transistor) sensors. EOSFET arrays are planar sensors capable of sensing the electrical activity of nearby neuron populations in both in vitro cultures and in vivo experiments. They are characterized by a high cell-like resolution and low invasiveness compared to probes with passive electrodes, but exhibit a higher noise power that requires ad hoc spike detection algorithms to detect relevant biological activity. Algorithms for implanted devices require good detection accuracy performance and low power consumption due to the limited power budget of implanted devices. A figure of merit (FoM) based on accuracy and resource consumption is presented and used to compare different algorithms present in the literature, such as the smoothed nonlinear energy operator and correlation-based algorithms. A multi transistor array (MTA) sensor of 7 honeycomb pixels of a 30 μm2 area is simulated, generating a signal with Neurocube. This signal is then used to validate the algorithms’ performances. The results allow us to numerically determine which is the most efficient algorithm in the case of power constraint in implantable devices and to characterize its performance in terms of accuracy and resource usage.

Low-Power Wearable Healthcare Sensors

Medical science has taken great steps to enable us to live longer and healthier lives [...]