Thermal Fatigue Modelling and Simulation of Flip Chip Component Solder Joints under Cyclic Thermal Loading

Study on Establishing Degradation Model of Chip Solder Joint Material under Coupled Stress

The chip is the core component of the integrated circuit. Degradation and failure of chip solder joints can directly lead to function loss of the integrated circuit. In order to establish the degradation model of chip solder joints under coupled stress, this paper takes quad flat package (QFP) chip solder joints as the study object. First, solder joint degradation data and failure samples were obtained through fatigue tests under coupled stress. Three types of micro failure modes of solder joints were obtained by scanning electron microscope (SEM) analysis and finite element model (FEM) simulation results. Second, the characterization of degradation data was obtained by the principal component of Mahalanobis distance (PCMD) algorithm. It is found that solder joint degradation is divided into three stages: strain accumulation stage, crack propagation stage, and failure stage. Later, Coffin–Manson model and Paris model were modified based on the PCMD health index and strain simulation. The function relationship between strain accumulation time, crack propagation time, and strain was determined, respectively. Solder joint degradation models at different degradation stage were established. Finally, through strain simulation, the models can predict the strain accumulation time and failure time effectively under each failure mode, and their prediction accuracy is above 85%.