Evaluation of In Vivo Spike Detection Algorithms for Implantable MTA Brain—Silicon Interfaces

From End to End: Gaining, Sorting, and Employing High-Density Neural Single Unit Recordings

The meaning behind neural single unit activity has constantly been a challenge, so it will persist in the foreseeable future. As one of the most sourced strategies, detecting neural activity in high-resolution neural sensor recordings and then attributing them to their corresponding source neurons correctly, namely the process of spike sorting, has been prevailing so far. Support from ever-improving recording techniques and sophisticated algorithms for extracting worthwhile information and abundance in clustering procedures turned spike sorting into an indispensable tool in electrophysiological analysis. This review attempts to illustrate that in all stages of spike sorting algorithms, the past 5 years innovations' brought about concepts, results, and questions worth sharing with even the non-expert user community. By thoroughly inspecting latest innovations in the field of neural sensors, recording procedures, and various spike sorting strategies, a skeletonization of relevant knowledge lays here, with an initiative to get one step closer to the original objective: deciphering and building in the sense of neural transcript.

Noise Power Minimization in CMOS Brain-Chip Interfaces

This paper presents specific noise minimization strategies to be adopted in silicon–cell interfaces. For this objective, a complete and general model for the analog processing of the signal coming from cell–silicon junctions is presented. This model will then be described at the level of the single stages and of the fundamental parameters that characterize them (bandwidth, gain and noise). Thanks to a few design equations, it will therefore be possible to simulate the behavior of a time-division multiplexed acquisition channel, including the most relevant parameters for signal processing, such as amplification (or power of the analog signal) and noise. This model has the undoubted advantage of being particularly simple to simulate and implement, while maintaining high accuracy in estimating the signal quality (i.e., the signal-to-noise ratio, SNR). Thanks to the simulation results of the model, it will be possible to set an optimal operating point for the front-end to minimize the artifacts introduced by the time-division multiplexing (TDM) scheme and to maximize the SNR at the a-to-d converter input. The proposed results provide an SNR of 12 dB at 10 µV_RMS of noise power and 50 µV_RMS of signal power (both evaluated at input of the analog front-end, AFE). This is particularly relevant for cell–silicon junctions because it demonstrates that it is possible to detect weak extracellular events (of the order of few µV_RMS) without necessarily increasing the total amplification of the front-end (and, therefore, as a first approximation, the dissipated electrical power), while adopting a specific gain distribution through the acquisition chain.

A Low Power 1024-Channels Spike Detector Using Latch-Based RAM for Real-Time Brain Silicon Interfaces

High-density microelectrode arrays allow the neuroscientist to study a wider neurons population, however, this causes an increase of communication bandwidth. Given the limited resources available for an implantable silicon interface, an on-fly data reduction is mandatory to stay within the power/area constraints. This can be accomplished by implementing a spike detector aiming at sending only the useful information about spikes. We show that the novel non-linear energy operator called ASO in combination with a simple but robust noise estimate, achieves a good trade-off between performance and consumption. The features of the investigated technique make it a good candidate for implantable BMIs. Our proposal is tested both on synthetic and real datasets providing a good sensibility at low SNR. We also provide a 1024-channels VLSI implementation using a Random-Access Memory composed by latches to reduce as much as possible the power consumptions. The final architecture occupies an area of 2.3 mm2, dissipating 3.6 µW per channels. The comparison with the state of art shows that our proposal finds a place among other methods presented in literature, certifying its suitability for BMIs.

Comparison of Sneo-Based Neural Spike Detection Algorithms for Implantable Multi-Transistor Array Biosensors

Real-time neural spike detection is an important step in understanding neurological activities and developing brain-silicon interfaces. Recent approaches exploit minimally invasive sensing techniques based on implanted complementary metal-oxide semiconductors (CMOS) multi transistors arrays (MTAs) that limit the damage of the neural tissue and provide high spatial resolution. Unfortunately, MTAs result in low signal-to-noise ratios due to the weak capacitive coupling between the nearby neurons and the sensor and the high noise power coming from the analog front-end. In this paper we investigate the performance achievable by using spike detection algorithms for MTAs, based on some variants of the smoothed non-linear energy operator (SNEO). We show that detection performance benefits from the correlation of the signals detected by the MTA pixels, but degrades when a high firing rate of neurons occurs. We present and compare different approaches and noise estimation techniques for the SNEO, aimed at increasing the detection accuracy at low SNR and making it less dependent on neurons firing rates. The algorithms are tested by using synthetic neural signals obtained with a modified version of NEUROCUBE generator. The proposed approaches outperform the SNEO, showing a more than 20% increase on averaged sensitivity at 0 dB and reduced dependence on the neuronal firing rate.