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Review on the Basic Circuit Elements and Memristor Interpretation: Analysis, Technology and Applications. JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS 2022. [DOI: 10.3390/jlpea12030044] [Citation(s) in RCA: 2] [Impact Index Per Article: 1.0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 12/10/2022]
Abstract
Circuit or electronic components are useful elements allowing the realization of different circuit functionalities. The resistor, capacitor and inductor represent the three commonly known basic passive circuit elements owing to their fundamental nature relating them to the four circuit variables, namely voltage, magnetic flux, current and electric charge. The memory resistor (or memristor) was claimed to be the fourth basic passive circuit element, complementing the resistor, capacitor and inductor. This paper presents a review on the four basic passive circuit elements. After a brief recall on the first three known basic passive circuit elements, a thorough description of the memristor follows. Memristor sparks interest in the scientific community due to its interesting features, for example nano-scalability, memory capability, conductance modulation, connection flexibility and compatibility with CMOS technology, etc. These features among many others are currently in high demand on an industrial scale. For this reason, thousands of memristor-based applications are reported. Hence, the paper presents an in-depth overview of the philosophical argumentations of memristor, technologies and applications.
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Wang R, Shi T, Zhang X, Wei J, Lu J, Zhu J, Wu Z, Liu Q, Liu M. Implementing in-situ self-organizing maps with memristor crossbar arrays for data mining and optimization. Nat Commun 2022; 13:2289. [PMID: 35484107 PMCID: PMC9051161 DOI: 10.1038/s41467-022-29411-4] [Citation(s) in RCA: 9] [Impact Index Per Article: 4.5] [Reference Citation Analysis] [Abstract] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 09/12/2021] [Accepted: 03/14/2022] [Indexed: 11/30/2022] Open
Abstract
A self-organizing map (SOM) is a powerful unsupervised learning neural network for analyzing high-dimensional data in various applications. However, hardware implementation of SOM is challenging because of the complexity in calculating the similarities and determining neighborhoods. We experimentally demonstrated a memristor-based SOM based on Ta/TaOx/Pt 1T1R chips for the first time, which has advantages in computing speed, throughput, and energy efficiency compared with the CMOS digital counterpart, by utilizing the topological structure of the array and physical laws for computing without complicated circuits. We employed additional rows in the crossbar arrays and identified the best matching units by directly calculating the similarities between the input vectors and the weight matrix in the hardware. Using the memristor-based SOM, we demonstrated data clustering, image processing and solved the traveling salesman problem with much-improved energy efficiency and computing throughput. The physical implementation of SOM in memristor crossbar arrays extends the capability of memristor-based neuromorphic computing systems in machine learning and artificial intelligence. Self-organizing maps are data mining tools for unsupervised learning algorithms dealing with big data problems. The authors experimentally demonstrate a memristor-based self-organizing map that is more efficient in computing speed and energy consumption for data clustering, image processing and solving optimization problems.
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Affiliation(s)
- Rui Wang
- The Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics Chinese Academy of Sciences, 100029, Beijing, PR China.,The Frontier institute of Chip and System, Fudan University, 200433, Shanghai, PR China.,University of Chinese Academy of Sciences, 100049, Beijing, PR China
| | - Tuo Shi
- The Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics Chinese Academy of Sciences, 100029, Beijing, PR China. .,University of Chinese Academy of Sciences, 100049, Beijing, PR China. .,Institute of Intelligent Computing, Zhejiang Laboratory, 311122, Hangzhou, PR China.
| | - Xumeng Zhang
- The Frontier institute of Chip and System, Fudan University, 200433, Shanghai, PR China
| | - Jinsong Wei
- The Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics Chinese Academy of Sciences, 100029, Beijing, PR China.,Institute of Intelligent Computing, Zhejiang Laboratory, 311122, Hangzhou, PR China
| | - Jian Lu
- The Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics Chinese Academy of Sciences, 100029, Beijing, PR China.,Institute of Intelligent Computing, Zhejiang Laboratory, 311122, Hangzhou, PR China
| | - Jiaxue Zhu
- The Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics Chinese Academy of Sciences, 100029, Beijing, PR China.,University of Chinese Academy of Sciences, 100049, Beijing, PR China
| | - Zuheng Wu
- The Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics Chinese Academy of Sciences, 100029, Beijing, PR China.,University of Chinese Academy of Sciences, 100049, Beijing, PR China
| | - Qi Liu
- The Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics Chinese Academy of Sciences, 100029, Beijing, PR China. .,The Frontier institute of Chip and System, Fudan University, 200433, Shanghai, PR China. .,University of Chinese Academy of Sciences, 100049, Beijing, PR China.
| | - Ming Liu
- The Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics Chinese Academy of Sciences, 100029, Beijing, PR China.,The Frontier institute of Chip and System, Fudan University, 200433, Shanghai, PR China.,University of Chinese Academy of Sciences, 100049, Beijing, PR China
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Liu MY, Chou W, Chien TW, Kuo SC, Yeh YT, Chou PH. Evaluating the research domain and achievement for a productive researcher who published 114 sole-author articles: A bibliometric analysis. Medicine (Baltimore) 2020; 99:e20334. [PMID: 32481321 PMCID: PMC7249850 DOI: 10.1097/md.0000000000020334] [Citation(s) in RCA: 9] [Impact Index Per Article: 2.3] [Reference Citation Analysis] [Abstract] [Key Words] [MESH Headings] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Submit a Manuscript] [Subscribe] [Scholar Register] [Indexed: 11/26/2022] Open
Abstract
BACKGROUND Team science research includes authors from various fields collaborating to publish their work on certain topics. Despite the numerous papers that discussed the ordering of author names and the contributions of authors to an article, no paper evaluatedIn addition, few researchers publish academic articles without co-author collaboration. Whether the bibliometric indexes (eg, h-/x-index) of sole-author researchers are higher than those of other types of multiple authors is required for comparison. We aimed to evaluate a productive author who published 114 sole-author articles with exceptional RA and RD in academics. METHODS By searching the PubMed database (Pubmed.com), we used the keyword of (Taiwan[affiliation]) from 2016 to 2017 and downloaded 29,356 articles. One physician (Dr. Tseng from the field of Internal Medicine) who published 12 articles as a single author was selected. His articles and citations were searched in PubMed. A comparison of various types of author ordering placements was conducted using sensitivity analysis to inspect whether this sole author earns the highest metrics in RA. Social network analysis (SNA), Gini coefficient (GC), pyramid plot, and the Kano diagram were applied to gather the following data for visualization: RESULTS:: We observed that CONCLUSIONS:: The metrics on RA are high for the sole author studied. The author's RD can be denoted by the MeSH terms and measured by the GC. The author-weighted scheme is required for quantifying author credits in an article to evaluate the author's RA. Social network analysis incorporating the Kano diagrams provided insights into the relationships between actors (eg, coauthors, MeSH terms, or journals). The methods used in this study can be replicated to evaluate other productive studies on RA and RD in the future.
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Affiliation(s)
- Mei-Yuan Liu
- Nutrition Department, Chi-Mei Medical Center
- Nutrition Department, Chang Jung Christian University, Tainan
- Department of Physical Medicine and Rehabilitation, Chung Shan Medical University, Taichun
| | - Willy Chou
- Department of Physical Medicine and Rehabilitation, Chung Shan Medical University, Taichun
- Department of Physical Medicine and Rehabilitation, Chiali Chi Mei Hospital
| | - Tsair-Wei Chien
- Department of Medical Research, Chi Mei Medical Center, Tainan, Taiwan
| | - Shu-Chun Kuo
- Department of Ophthalmology, Chi-Mei Medical Center
- Department of Optometry, Chung Hwa University of Medical Technology, Jen-Teh, Tainan City, Taiwan
| | - Yu-Tsen Yeh
- Medical School, St. George's, University of London, London, United Kingdom
| | - Po-Hsin Chou
- Department of Orthopedics and Traumatology, Taipei Veterans General Hospital
- School of Medicine, National Yang-Ming University, Taipei, Taiwan
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Memristors for Neuromorphic Circuits and Artificial Intelligence Applications. MATERIALS 2020; 13:ma13040938. [PMID: 32093164 PMCID: PMC7078602 DOI: 10.3390/ma13040938] [Citation(s) in RCA: 15] [Impact Index Per Article: 3.8] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Download PDF] [Subscribe] [Scholar Register] [Received: 01/18/2020] [Accepted: 01/30/2020] [Indexed: 12/16/2022]
Abstract
Artificial Intelligence has found many applications in the last decade due to increased computing power. Artificial Neural Networks are inspired in the brain structure and consist in the interconnection of artificial neurons through artificial synapses in the so-called Deep Neural Networks (DNNs). Training these systems requires huge amounts of data and, after the network is trained, it can recognize unforeseen data and provide useful information. As far as the training is concerned, we can distinguish between supervised and unsupervised learning. The former requires labelled data and is based on the iterative minimization of the output error using the stochastic gradient descent method followed by the recalculation of the strength of the synaptic connections (weights) with the backpropagation algorithm. On the other hand, unsupervised learning does not require data labeling and it is not based on explicit output error minimization. Conventional ANNs can function with supervised learning algorithms (perceptrons, multi-layer perceptrons, convolutional networks, etc.) but also with unsupervised learning rules (Kohonen networks, self-organizing maps, etc.). Besides, another type of neural networks are the so-called Spiking Neural Networks (SNNs) in which learning takes place through the superposition of voltage spikes launched by the neurons. Their behavior is much closer to the brain functioning mechanisms they can be used with supervised and unsupervised learning rules. Since learning and inference is based on short voltage spikes, energy efficiency improves substantially. Up to this moment, all these ANNs (spiking and conventional) have been implemented as software tools running on conventional computing units based on the von Neumann architecture. However, this approach reaches important limits due to the required computing power, physical size and energy consumption. This is particularly true for applications at the edge of the internet. Thus, there is an increasing interest in developing AI tools directly implemented in hardware for this type of applications. The first hardware demonstrations have been based on Complementary Metal-Oxide-Semiconductor (CMOS) circuits and specific communication protocols. However, to further increase training speed andenergy efficiency while reducing the system size, the combination of CMOS neuron circuits with memristor synapses is now being explored. It has also been pointed out that the short time non-volatility of some memristors may even allow fabricating purely memristive ANNs. The memristor is a new device (first demonstrated in solid-state in 2008) which behaves as a resistor with memory and which has been shown to have potentiation and depression properties similar to those of biological synapses. In this Special Issue, we explore the state of the art of neuromorphic circuits implementing neural networks with memristors for AI applications.
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