Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications

Bipolar Resistive Switching in TiO2 Artificial Synapse Mimicking Pavlov's Associative Learning

Memristive devices are among the most emerging electronic elements to realize artificial synapses for neuromorphic computing (NC) applications and have potential to replace the traditional von-Neumann computing architecture in recent times. In this work, pulsed laser deposition-manufactured Ag/TiO₂/Pt memristor devices exhibiting digital and analog switching behavior are considered for NC. The TiO₂ memristor shows excellent performance of digital resistive switching with a memory window of order ∼10³. Furthermore, the analog resistive switching offers multiple conductance levels supporting the development of the bioinspired synapse. A possible mechanism for digital and analog switching behavior in our device is proposed. Remarkably, essential synaptic functions such as pair-pulse facilitation, long-term potentiation (LTP), and long-term depression (LTD) are successfully realized based on the change in conductance through analog memory characteristics. Based on the LTP-LTD, a neural network simulation for the pattern recognition task using the MNIST data set is investigated, which shows a high recognition accuracy of 95.98%. Furthermore, more complex synaptic behavior such as spike-time-dependent plasticity and Pavlovian classical conditioning is successfully emulated for associative learning of the biological brain. This work enriches the TiO₂-based resistive random-access memory, which provides information about the simultaneous existence of digital and analog behavior, thereby facilitating the further implementation of memristors in low-power NC.

A Vertical Single Transistor Neuron with Core-Shell Dual-Gate for Excitatory-Inhibitory Function and Tunable Firing Threshold Voltage

A novel inhibitable and firing threshold voltage tunable vertical nanowire (NW) single transistor neuron device with core-shell dual-gate (CSDG) was realized and verified by TCAD simulation. The CSDG NW neuron is enclosed by an independently accessed shell gate and core gate to serve an excitatory-inhibitory transition and a firing threshold voltage adjustment, respectively. By utilizing the shell gate, the firing of specific neuron can be inhibited for winner-takes-all learning. It was confirmed that the independently accessed core gate can be used for adjustment of the firing threshold voltage to compensate random conductance variation before the learning and to fix inference error caused by unwanted synapse conductance change after the learning. This threshold voltage tuning can also be utilized for homeostatic function during the learning process. Furthermore, a myelination function which controls the transmission rate was obtained based on the inherent asymmetry between the source and drain in vertical NW structure. Finally, using the CSDG NW neuron device, a letter recognition test was conducted by SPICE simulation for a system-level validation. This multi-functional neuron device can contribute to construct a high-density monolithic SNN hardware combining with the previously developed vertical synapse MOSFET devices.

Optimization of the structural complexity of artificial neural network for hardware-driven neuromorphic computing application

This work focuses on the optimization of the structural complexity of a single-layer feedforward neural network (SLFN) for neuromorphic hardware implementation. The singular value decomposition (SVD) method is used for the determination of the effective number of neurons in the hidden layer for Modified National Institute of Standards and Technology (MNIST) dataset classification. The proposed method is also verified on a SLFN using weights derived from a synaptic transistor device. The effectiveness of this methodology in estimating the reduced number of neurons in the hidden layer makes this method highly useful in optimizing complex neural network architectures for their hardware realization.

Medium-Temperature-Oxidized GeOx Resistive-Switching Random-Access Memory and Its Applicability in Processing-in-Memory Computing

Processing-in-memory (PIM) is emerging as a new computing paradigm to replace the existing von Neumann computer architecture for data-intensive processing. For the higher end-user mobility, low-power operation capability is more increasingly required and components need to be renovated to make a way out of the conventional software-driven artificial intelligence. In this work, we investigate the hardware performances of PIM architecture that can be presumably constructed by resistive-switching random-access memory (ReRAM) synapse fabricated with a relatively larger thermal budget in the full Si processing compatibility. By introducing a medium-temperature oxidation in which the sputtered Ge atoms are oxidized at a relatively higher temperature compared with the ReRAM devices fabricated by physical vapor deposition at room temperature, higher device reliability has been acquired. Based on the empirically obtained device parameters, a PIM architecture has been conceived and a system-level evaluations have been performed in this work. Considerations include the cycle-to-cycle variation in the GeO_x ReRAM synapse, analog-to-digital converter resolution, synaptic array size, and interconnect latency for the system-level evaluation with the Canadian Institute for Advance Research-10 dataset. A fully Si processing-compatible and robust ReRAM synapse and its applicability for PIM are demonstrated.

Emulation of synaptic functions with low voltage organic memtransistor for hardware oriented neuromorphic computing

Here, various synaptic functions and neural network simulation based pattern-recognition using novel, solution-processed organic memtransistors (memTs) with an unconventional redox-gating mechanism are demonstrated. Our synaptic memT device using conjugated polymer thin-film and redox-active solid electrolyte as the gate dielectric can be routinely operated at gate voltages (V_GS) below − 1.5 V, subthreshold-swings (S) smaller than 120 mV/dec, and ON/OFF current ratio larger than 10⁸. Large hysteresis in transfer curves depicts the signature of non-volatile resistive switching (RS) property with ON/OFF ratio as high as 10⁵. In addition, our memT device also shows many synaptic functions, including the availability of many conducting-states (> 500) that are used for efficient pattern recognition using the simplest neural network simulation model with training and test accuracy higher than 90%. Overall, the presented approach opens a new and promising way to fabricate high-performance artificial synapses and their arrays for the implementation of hardware-oriented neural network.