Low-Power OR Logic Ferroelectric In-Situ Transistor Based on a CuInP2S6/MoS2 Van Der Waals Heterojunction

Eliminating Ferroelectric Hysteresis in All-Two-Dimensional Gate-Stack Negative-Capacitance Transistors

Boltzmann distribution thermal tails of carriers restrain the subthreshold swing (SS) of field-effect transistors (FETs) to be lower than 60 mV/decade at room temperature, which restrains the reduction of operate-voltage and power consumption of transistors. The negative-capacitance FET (NC FET) is expected to break through this physical limit and obtain a steep SS by amplifying the gate voltage through the negative capacitance effect of the ferroelectric thin film, providing a new way to further reduce the power consumption of the transistor at the end of Moore's law. Here, we show a MoS2 NC FET with a CuInP2S6 ferroelectric, exhibiting a large on/off ratio of 108, a steep SS as low as 6 mV/decade, and a wide sub-60 mV/decade drain current range of more than 4 orders of magnitude while sacrificially inducing a huge hysteresis larger than 500 mV. Furthermore, we found that by inserting the h-phase boron nitride (h-BN) layer with suitable thickness, the dielectric capacitance matches the ferroelectric negative capacitance better, and thus the hysteresis on the transfer curve is reduced, and the ideal switching-behavior transistors with SS as low as 62 mV/decade and only 5 mV negligible hysteresis were obtained. Our work demonstrates that under the capacitance-matching condition, the hysteresis-free negative-capacitance transistors do not act as the predicted steep-slope transistors, but their voltage-saving still occurs instead as a type of effective transconductance booster with more than 20 times transconductance amplification.

Large Memory Window of van der Waals Heterostructure Devices Based on MOCVD-Grown 2D Layered Ge4 Se9

Van der Waals (vdW) heterostructures have drawn much interest over the last decade owing to their absence of dangling bonds and their intriguing low-dimensional properties. The emergence of 2D materials has enabled the achievement of significant progress in both the discovery of physical phenomena and the realization of superior devices. In this work, the group IV metal chalcogenide 2D-layered Ge₄ Se₉ is introduced as a new selection of insulating vdW material. 2D-layered Ge₄ Se₉ is synthesized with a rectangular shape using the metalcorganic chemical vapor deposition system using a liquid germanium precursor at 240 °C. By stacking the Ge₄ Se₉ and MoS₂ , vdW heterostructure devices are fabricated with a giant memory window of 129 V by sweeping back gate range of ±80 V. The gate-independent decay time reveals that the large hysteresis is induced by the interfacial charge transfer, which originates from the low band offset. Moreover, repeatable conductance changes are observed over the 2250 pulses with low non-linearity values of 0.26 and 0.95 for potentiation and depression curves, respectively. The energy consumption of the MoS₂ /Ge₄ Se₉ device is about 15 fJ for operating energy and the learning accuracy of image classification reaches 88.3%, which further proves the great potential of artificial synapses.

Ferroelectrics-Integrated Two-Dimensional Devices toward Next-Generation Electronics

Ferroelectric materials play an important role in a wide spectrum of semiconductor technologies and device applications. Two-dimensional (2D) van der Waals (vdW) ferroelectrics with surface-insensitive ferroelectricity that is significantly different from their traditional bulk counterparts have further inspired intensive interest. Integration of ferroelectrics into 2D-layered-material-based devices is expected to offer intriguing working principles and add desired functionalities for next-generation electronics. Herein, fundamental properties of ferroelectric materials that are compatible with 2D devices are introduced, followed by a critical review of recent advances on the integration of ferroelectrics into 2D devices. Representative device architectures and corresponding working mechanisms are discussed, such as ferroelectrics/2D semiconductor heterostructures, 2D ferroelectric tunnel junctions, and 2D ferroelectric diodes. By leveraging the favorable properties of ferroelectrics, a variety of functional 2D devices including ferroelectric-gated negative capacitance field-effect transistors, programmable devices, nonvolatile memories, and neuromorphic devices are highlighted, where the application of 2D vdW ferroelectrics is particularly emphasized. This review provides a comprehensive understanding of ferroelectrics-integrated 2D devices and discusses the challenges of applying them into commercial electronic circuits.