GFET Asymmetric Transfer Response Analysis through Access Region Resistances

Reconfigurable frequency multipliers based on graphene field-effect transistors

Run-time device-level reconfigurability has the potential to boost the performance and functionality of numerous circuits beyond the limits imposed by the integration density. The key ingredient for the implementation of reconfigurable electronics lies in ambipolarity, which is easily accessible in a substantial number of two-dimensional materials, either by contact engineering or architecture device-level design. In this work, we showcase graphene as an optimal solution to implement high-frequency reconfigurable electronics. We propose and analyze a split-gate graphene field-effect transistor, demonstrating its capability to perform as a dynamically tunable frequency multiplier. The study is based on a physically based numerical simulator validated and tested against experiments. The proposed architecture is evaluated in terms of its performance as a tunable frequency multiplier, able to switch between doubler, tripler or quadrupler operation modes. Different material and device parameters are analyzed, and their impact is assessed in terms of the reconfigurable graphene frequency multiplier performance.

Superconducting- and Graphene-Based Devices

This Special Issue has been organized to collect new or improved ideas regarding the exploitation of superconducting materials, as well as graphene, aiming to develop innovative devices [...].

Unveiling the impact of the bias-dependent charge neutrality point on graphene based multi-transistor applications

The Dirac voltage of a graphene field-effect transistor (GFET) stands for the gate bias that sets the charge neutrality condition in the channel, thus resulting in a minimum conductivity. Controlling its dependence on the terminal biases is crucial for the design and optimization of radio-frequency applications based on multiple GFETs. However, the previous analysis of such dependence carried out for single devices is uncomplete and if not properly understood could result in circuit designs with poor performance. The control of the Dirac point shift (DPS) is particularly important for the deployment of graphene-based differential circuit topologies where keeping a strict symmetry between the electrically balanced branches is essential for exploiting the advantages of such topologies. This note sheds light on the impact of terminal biases on the DPS in a real device and sets a rigorous methodology to control it so to eventually optimize and exploit the performance of radio-frequency applications based on GFETs.

Multi-scale analysis of radio-frequency performance of 2D-material based field-effect transistors

Two-dimensional materials (2DMs) are a promising alternative to complement and upgrade high-frequency electronics. However, in order to boost their adoption, the availability of numerical tools and physically-based models able to support the experimental activities and to provide them with useful guidelines becomes essential. In this context, we propose a theoretical approach that combines numerical simulations and small-signal modeling to analyze 2DM-based FETs for radio-frequency applications. This multi-scale scheme takes into account non-idealities, such as interface traps, carrier velocity saturation, or short channel effects, by means of self-consistent physics-based numerical calculations that later feed the circuit level via a small-signal model based on the dynamic intrinsic capacitances of the device. At the circuit stage, the possibilities range from the evaluation of the performance of a single device to the design of complex circuits combining multiple transistors. In this work, we validate our scheme against experimental results and exemplify its use and capability assessing the impact of the channel scaling on the performance of MoS₂-based FETs targeting RF applications.

Contact resistance and mobility in back-gate graphene transistors

The metal-graphene contact resistance is one of the major limiting factors toward the technological exploitation of graphene in electronic devices and sensors. High contact resistance can be detrimental to device performance and spoil the intrinsic great properties of graphene. In this paper, we fabricate back-gate graphene field-effect transistors with different geometries to study the contact and channel resistance as well as the carrier mobility as a function of gate voltage and temperature. We apply the transfer length method and the y-function method showing that the two approaches can complement each other to evaluate the contact resistance and prevent artifacts in the estimation of carrier mobility dependence on the gate-voltage. We find that the gate voltage modulates both the contact and the channel resistance in a similar way but does not change the carrier mobility. We also show that raising the temperature lowers the carrier mobility, has a negligible effect on the contact resistance, and can induce a transition from a semiconducting to a metallic behavior of the graphene sheet resistance, depending on the applied gate voltage. Finally, we show that eliminating the detrimental effects of the contact resistance on the transistor channel current almost doubles the carrier field-effect mobility and that a competitive contact resistance as low as 700 Ω·μm can be achieved by the zig-zag shaping of the Ni contact.