Design of Reconfigurable Time-to-Digital Converter Based on Cascaded Time Interpolators for Electrical Impedance Spectroscopy

Wearable and Noninvasive Device for Integral Congestive Heart Failure Management in the IoMT Paradigm

Noninvasive remote monitoring of hemodynamic variables is essential in optimizing treatment opportunities and predicting rehospitalization in patients with congestive heart failure. The objective of this study is to develop a wearable bioimpedance-based device, which can provide continuous measurement of cardiac output and stroke volume, as well as other physiological parameters for a greater prognosis and prevention of congestive heart failure. The bioimpedance system, which is based on a robust and cost-effective measuring principle, was implemented in a CMOS application specific integrated circuit, and operates as the analog front-end of the device, which has been provided with a radio-frequency section for wireless communication. The operating parameters of the proposed wearable device are remotely configured through a graphical user interface to measure the magnitude and the phase of complex impedances over a bandwidth of 1 kHz to 1 MHz. As a result of this study, a cardiac activity monitor was implemented, and its accuracy was evaluated in 33 patients with different heart diseases, ages, and genders. The proposed device was compared with a well-established technique such as Doppler echocardiography, and the results showed that the two instruments are clinically equivalent.

On-Chip Sinusoidal Signal Generators for Electrical Impedance Spectroscopy: Methodological Review

This paper reviews architectures and circuit implementations of on-chip sinusoidal signal generators (SSGs) for electrical impedance spectroscopy (EIS) applications. In recent years, there have been increasing interests in on-chip EIS systems, which measure a target material's impedance spectrum over a frequency range. The on-chip implementation allows EIS systems to have low power and small form factor, enabling various biomedical applications. One of the key building blocks of on-chip EIS systems is on-chip SSG, which determines the frequency range and the analysis precision of the whole EIS system. On-chip SSGs are generally required to have high linearity, wide frequency range, and high power and area efficiency. They are typically composed of three stages in general: waveform generation, linearity enhancement, and current injection. First, a sinusoidal waveform should be generated in SSGs. The generated waveform's frequency should be accurately adjustable over a wide range. The firstly generated waveform may not be perfectly linear, including unwanted harmonics. In the following linearity-enhancement step, these harmonics are attenuated by using filters typically. As the linearity of the waveform is improved, the precision of the EIS system gets ensured. Lastly, the filtered voltage waveform is now converted to a current by a current driver. Then, the current sinusoidal signal is injected into the target impedance. This review discusses the principles, advantages, and disadvantages of various techniques applied to each step in state-of-the-art on-chip SSGs. In addition, state-of-the-art designs are compared and summarized.

An Impedance Readout IC with Ratio-Based Measurement Techniques for Electrical Impedance Spectroscopy

This paper presents an error-tolerant and power-efficient impedance measurement scheme for bioimpedance acquisition. The proposed architecture measures the magnitude and the real part of the target complex impedance, unlike other impedance measurement architectures measuring either the real/imaginary components or the magnitude and phase. The phase information of the target impedance is obtained by using the ratio between the magnitude and the real components. This can allow for avoiding direct phase measurements, which require fast, power-hungry circuit blocks. A reference resistor is connected in series with the target impedance to compensate for the errors caused by the delay in the sinusoidal signal generator and the amplifier at the front. Moreover, an additional magnitude measurement path is connected to the reference resistor to cancel out the nonlinearity of the proposed system and enhance the settling speed of the low-pass filter by a ratio-based detection. Thanks to this ratio-based detection, the accuracy is enhanced by 30%, and the settling time is improved by 87.7% compared to the conventional single-path detection. The proposed integrated circuit consumes only 513 μW for a wide frequency range of 10 Hz to 1 MHz, with the maximum magnitude and phase errors of 0.3% and 2.1°, respectively.

A Polar-Demodulation-Based Impedance-Measurement IC Using Frequency-Shift Technique With Low Power Consumption and Wide Frequency Range

In this paper, we present a new impedance measurement integrated circuit (IC) for achieving a wideband coverage up to 10 MHz and low power consumption. A frequency-shift technique is applied to down-shift the input frequency, which ranges from 100 kHz to 10 MHz, into an intermediate frequency of 10 kHz, while the frequency-shifting is bypassed when the input frequency falls in the range from 100 Hz to 100 kHz. It results in 100 times relaxation of the requirement on the instrumentation amplifier (IA) bandwidth and the comparator delay, greatly reducing overall power consumption. The proposed IC employs the polar demodulation structure with a reference resistor that provides reference timing information avoiding any synchronization issue with the transmitter. In order to compensate for the comparator delay and nonlinearity of the IA, the reference magnitude measurement path is added, making only the mismatch of the circuit affects the accuracy. This allows for employing the auto-zeroing technique that can remove the offset but increase the absolute delay by using an additional capacitor to the comparator. The chip fabricated in a 0.18- μm CMOS technology consumes the power of 756 μW while covering the measurement frequency range from 100 Hz to 10 MHz and exhibiting the maximum magnitude and phase errors of 1.1 % and 1.9 ^°, respectively.

Time Stamp - A Novel Time-to-Digital Demodulation Method for Bioimpedance Implant Applications

Bioimpedance analysis is a noninvasive and inexpensive technology used to investigate the electrical properties of biological tissues. The analysis requires demodulation to extract the real and imaginary parts of the impedance. Conventional systems use complex architectures such as I-Q demodulation. In this paper, a very simple alternative time-to-digital demodulation method or 'time stamp' is proposed. It employs only three comparators to identify or stamp in the time domain, the crossing points of the excitation signal, and the measured signal. In a CMOS proof of concept design, the accuracy of impedance magnitude and phase is 97.06% and 98.81% respectively over a bandwidth of 10 kHz to 500 kHz. The effect of fractional-N synthesis is analysed for the counter-based zero crossing phase detector obtaining a finer phase resolution (0.51˚ at 500 kHz) using a counter clock frequency ( f_clk = 12.5 MHz). Because of its circuit simplicity and ease of transmitting the time stamps, the method is very suited to implantable devices requiring low area and power consumption.