Exploring memory synchronization and performance considerations for FPGA platform using the high-abstracted OpenCL framework: Benchmarks development and analysis

A key benefit of the Open Computing Language (OpenCL) software framework is its capability to operate across diverse architectures. Field programmable gate arrays (FPGAs) are a high-speed computing architecture used for computation acceleration. This study investigates the impact of memory access time on overall performance in general FPGA computing environments through the creation of eight benchmarks within the OpenCL framework. The developed benchmarks capture a range of memory access behaviors, and they play a crucial role in assessing the performance of spinning and sleeping on FPGA-based architectures. The results obtained guide the formulation of new implementations and contribute to defining an abstraction of FPGAs. This abstraction is then utilized to create tailored implementations of primitives that are well-suited for this platform. While other research endeavors concentrate on creating benchmarks with the Compute Unified Device Architecture (CUDA) to scrutinize the memory systems across diverse GPU architectures and propose recommendations for future generations of GPU computation platforms, this study delves into the memory system analysis for the broader FPGA computing platform. It achieves this by employing the highly abstracted OpenCL framework, exploring various data workload characteristics, and experimentally delineating the appropriate implementation of primitives that can seamlessly integrate into a design tailored for the FPGA computing platform. Additionally, the results underscore the efficacy of employing a task-parallel model to mitigate the need for high-cost synchronization mechanisms in designs constructed on general FPGA computing platforms.

A New Optimized Hybridization Approach for in silico High Throughput Molecular Docking on FPGA Platform

BACKGROUND

The development process of a new drug should be a subject of continuous evolution and rapid improvement as drugs are essential to treat a wide range of diseases of which many are life-threatening. The advances in technology resulted in a novel track in drug discovery and development known as in silico drug design. The molecular docking phase plays a vital role in in silico drug development process. In this phase, thousands of 3D conformations of both the ligand and receptor are generated and the best conformations that create the most stable drug-receptor complex are determined. The speed in finding accurate and high-quality complexes depends on the efficiency of the search function in the molecular docking procedure.

OBJECTIVE

The objective of this research is to propose and implement a novel hybrid approach called hABCDE to replace the EMC searching part inside the BUDE docking algorithm. This helps in reaching the best solution in a much accelerated time and higher solution quality compared to using the ABC and DE algorithms separately.

METHODS

In this work, we have employed a new approach of hybridization between the Artificial Bee Colony (ABC) algorithm and the Differential Evolution (DE) algorithm as an alternative searching part of the Bristol University Docking Engine (BUDE) in order to accelerate the search for higher quality solutions. Moreover, the proposed docking approach was implemented on Field Programmable Gate Array (FPGA) parallel platform using Vivado High-Level Synthesis Tool (HLST) in order to optimize and enhance the execution time and overall efficiency. The NDM-1 protein was used as a model receptor in our experiments to demonstrate the efficiency of our approach.

RESULTS

The NDM-1 protein was used as a model receptor in our experiments to demonstrate the efficiency of our approach. The results showed that the execution time for the BUDE with the new proposed hybridization approach was improved by 9,236 times.

CONCLUSION

Our novel approach was significantly effective to improve the functionality of docking algorithms (Bristol University Docking Engine (BUDE)).

An OpenCL-based parallel acceleration of aSobel edge detection algorithm Using IntelFPGA technology

This paper examines the feasibility of using commercial out-of-the-box Reconfigurable Field Programmable Gate Array (FPGA) technology and the OpenCL framework to create efficient Sobel edge-detection implementation, which is considered a fundamental part in the field of image and video processing. The revised proposed approach was created at a high level of abstraction and executed on high commodity Intel FPGA platform. This was performed in a manner that was designed to allow the high-level compiler/synthesis tool to manipulate a task a parallelism model. The most promising FPGA and the naive implementations were compared to their single-core CPU software equivalents while manipulating local-memory, pipelining, loop unrolling, vectorization, internal channels mechanisms and memory coalescing to provide a much more effective hardware design. The run-time and the power consumption attributes were estimated for each implementation. The proposed FPGA based implementations were found to have significantly better runtime and power consumption with approximately up to 37 folds of improvement in the whole execution/transfer time, and up to 53 folds of improvement in energy consumption when compared to a specific single-core CPU based implementation.

Short communication: Effects of processing methods of barley grain in starter diets on feed intake and performance of dairy calves

The present study was conducted to evaluate the effects of different processing methods of barley grain in starter rations on feed intake, average daily gain, feed efficiency, skeletal growth, fecal score, and rumen pH of dairy calves. Thirty-two Holstein dairy calves (16 female and 16 male) were randomly allocated to 1 of 4 treatments consisting of coarse ground, whole, steam-rolled, or roasted barley from d 4 to 56 of birth in a completely randomized design. Starter diets were formulated to have similar ingredients and composition. All calves had free access to water and feed throughout the study period and received 4 L of milk/d from a bottle from d 4 to 41, 2L/d from d 41 to 45, and weaning occurred on d 45. Feed intake and fecal score were recorded daily. Body weight and skeletal growth measures were recorded on d 4 (beginning of the study), 45, and 56. Rumen fluid and blood samples were collected on d 35, 45, and 56. Data were analyzed using PROC MIXED of SAS (SAS Institute Inc., Cary, NC). The results indicate that different methods of processing barley had no detectable effect on dry matter intake, average daily gain, and feed efficiency and that skeletal growth, health, and rumen pH were not affected by dietary treatments. In conclusion, the results show that different processing methods of barley included in starter diets had no detectable effect on the performance of dairy calves under our experimental conditions. Therefore, feeding whole or coarsely ground barley would be a more economical method compared with steam rolled or roasted barley.

Reverse engineering of dynamic networks

We consider the problem of reverse-engineering dynamic models of biochemical networks from experimental data using polynomial dynamic systems. In earlier work, we developed an algorithm to identify minimal wiring diagrams, that is, directed graphs that represent the causal relationships between network variables. Here we extend this algorithm to identify a most likely dynamic model from the set of all possible dynamic models that fit the data over a fixed wiring diagram. To illustrate its performance, the method is applied to simulated time-course data from a published gene regulatory network in the fruitfly Drosophila melanogaster.