Dust-Sized High-Power-Density Photovoltaic Cells on Si and SOI Substrates for Wafer-Level-Packaged Small Edge Computers

Advancement in microelectronics technology enables autonomous edge computing platforms in the size of a dust mote (<1 mm), bringing efficient and low-cost artificial intelligence close to the end user and Internet-of-Things (IoT) applications. The key challenge for these compact high-performance edge computers is the integration of a power source that satisfies the high-power-density requirement and does not increase the complexity and cost of the packaging. Here, it is shown that dust-sized III-V photovoltaic (PV) cells grown on Si and silicon-on-insulator (SOI) substrates can be integrated using a wafer-level-packaging process and achieve higher power density than all prior micro-PVs on Si and SOI substrates. The high-throughput heterogeneous integration unlocks the potential of large-scale manufacturing of these integrated systems with low cost for IoT applications. The negative effect of crystallographic defects in the heteroepitaxial materials on PV performance diminishes at high power density. Simultaneous power delivery and data transmission to the dust mote with heteroepitaxially grown PV are also demonstrated using hand-held illumination sources.

Single Crystal Flexible Electronics Enabled by 3D Spalling

Flexible and stretchable electronics are becoming increasingly important in many emerging applications. Due to the outstanding electrical properties of single crystal semiconductors, there is great interest in releasing single crystal thin films and fabricating flexible electronics with these conventionally rigid materials. In this study the authors report a universal single crystal layer release process, called "3D spalling," extending beyond prior art. In contrast to the conventional way of removing blanket layers from their substrates, the new process reported here enables 3D control over the shape and thickness of the removed regions, allowing direct formation of arbitrarily shaped structures of released film and locally specified thickness for each region. As an exemplary demonstration, silicon flexible tactile sensors are fabricated with sensitivities comparable to those of high performance sensors on rigid substrates. Finite element modeling indicates that the size and thickness of the selectively released features can be tuned over a wide range.

9.4% efficient amorphous silicon solar cell on high aspect-ratio glass microcones

High aspect-ratio three-dimensional (3D) a-Si:H solar cells have been fabricated to enhance a light absorption path while maintaining a short carrier collection length. Substantial efficiency enhancement in 3D solar cells was achieved due to the boost in JSC with no degradation of FF which is comparable to FF obtained from 2D solar cells.