Crystalline Si Surface Passivation with Nafion for Bulk Defects Detection with Electron Paramagnetic Resonance

In monocrystalline Si (c-Si) solar cells, identification and mitigation of bulk defects are crucial to achieving a high photoconversion efficiency. To spectroscopically detect defects in the c-Si bulk, it is desirable to passivate the surface defects. Passivation of the c-Si surface with dielectrics such as Al2O3 and SiNx requires deposition at elevated temperatures, which can influence defects in the bulk. Herein, we report on the passivation of different Czochralski (Cz) Si wafer surfaces by an organic copolymer, Nafion. We test the efficacy of the surface passivation at temperatures ranging from 6 to 473 K to detect bulk defects using electron paramagnetic resonance (EPR) spectroscopy. By comparing with state-of-the-art passivation layers, including Al2O3 and liquid HF/HCl, we found that at room temperature, Nafion can provide comparable passivation of n-type Cz Si with an implied open-circuit voltage (iVoc) of 713 mV and a recombination current prefactor J0 of 5 fA/cm2. For p-type Cz Si, we obtained an iVoc of 682 mV with a J0 of 22.4 fA/cm2. Scanning electron microscopy and photoluminescence reveal that Nafion can also be used to passivate the surface of c-Si solar cell fragments scribed from a solar cell module by using a laser. Consistent with previous studies, analysis of the EPR spectroscopy data confirms that the H-terminated surface is necessary, and fixed negative charge in Nafion is responsible for the field-effect passivation. While the surface passivation quality was maintained for almost 24 h, which is sufficient for spectroscopic measurements, the passivation degraded over longer durations, which can be attributed to surface SiOx growth. These results show that Nafion is a promising room-temperature surface passivation technique to study bulk defects in c-Si.

Effect of Surface Texture on Pinhole Formation in SiOx-Based Passivated Contacts for High-Performance Silicon Solar Cells

High-efficiency silicon solar cells rely on some form of passivating contact structure to reduce recombination losses at the crystalline silicon surface and losses at the metal/Si contact interface. One such structure is polycrystalline silicon (poly-Si) on oxide, where heavily doped poly-Si is deposited on a SiO_x layer grown directly on the crystalline silicon (c-Si) wafer. Depending on the thickness of the SiO_x layer, the charge carriers can cross this layer by tunneling (<2 nm SiO_x thickness) or by direct conduction through disruptions in the SiO_x, often referred to as pinholes, in thicker SiO_x layers (>2 nm). In this work, we study structures with tunneling- or pinhole-like SiO_x contacts grown on pyramidally textured c-Si wafers and expose variations in the SiO_x layer properties related to surface morphology using electron-beam-induced current (EBIC) imaging. Using EBIC, we identify and mark regions with potential pinholes in the SiO_x layer. We further perform high-resolution transmission electron microscopy on the same areas, thus allowing us to directly correlate locally enhanced carrier collection with variations in the structure of the SiO_x layer. Our results show that the pinholes in the SiO_x layer preferentially form in different locations based on the annealing conditions used to form the device. With greater understanding of these processes and by controlling the surface texture geometry, there is potential to control the size and spatial distribution of oxide disruptions in silicon solar cells with poly-Si on oxide-type contacts; usually, this is a random phenomenon on polished or planar surfaces. Such control will enable us to consistently produce high-efficiency devices with low recombination currents and low junction resistances using this contact structure.

Effect of Crystallographic Orientation and Nanoscale Surface Morphology on Poly-Si/SiOx Contacts for Silicon Solar Cells

High-efficiency crystalline silicon (Si) solar cells require textured surfaces for efficient light trapping. However, passivation of a textured surface to reduce carrier recombination is difficult. Here, we relate the electrical properties of cells fabricated on a KOH-etched, random pyramidal-textured Si surface to the nanostructure of the passivated contact and the textured surface morphology. The effects of both microscopic pyramidal morphology and nanoscale surface roughness on passivated contacts consisting of polycrystalline Si (poly-Si) deposited on top of an ultrathin, 1.5-2.2 nm, SiO_x layer are investigated. Using atomic force microscopy, we show a pyramid face, which is predominantly a Si(111) plane to be significantly rougher than a polished Si(111) surface. This roughness results in a nonuniform SiO_x layer as determined by transmission electron microscopy of a poly-Si/SiO_x contact. Our device measurements also show an overall more resistive and hence a thicker SiO_x layer over the pyramidal surface as compared to a polished Si(111) surface, which we relate to increased surface roughness. Using electron-beam-induced current measurements of poly-Si/SiO_x contacts, we further show that the SiO_x layer near the pyramid valleys is preferentially more conducting and hence likely thinner than over pyramid tips, edges, and faces. Hence, both the microscopic pyramidal morphology and nanoscale roughness lead to a nonuniform SiO_x layer, thus leading to poor poly-Si/SiO_x contact passivation. Finally, we report >21% efficient and ≥80% fill-factor front/back poly-Si/SiO_x solar cells on both single-side and double-side textured wafers without the use of transparent conductive oxide layers, and show that the poorer contact passivation on a textured surface is limited to boron-doped poly-Si/SiO_x contacts.

From amorphous to nanocrystalline: the effect of nanograins in an amorphous matrix on the thermal conductivity of hot-wire chemical-vapor deposited silicon films

We have measured the thermal conductivity of amorphous and nanocrystalline silicon films with varying crystalline content from 85 K to room temperature. The films were prepared by the hot-wire chemical-vapor deposition, where the crystalline volume fraction is determined by the hydrogen (H₂) dilution ratio to the processing silane gas (SiH₄), R  =  H₂/SiH₄. We varied R from 1 to 10, where the films transform from amorphous for R  <  3 to mostly nanocrystalline for larger R. Structural analyses show that the nanograins, averaging from 2 to 9 nm in sizes with increasing R, are dispersed in the amorphous matrix. The crystalline volume fraction increases from 0 to 65% as R increases from 1 to 10. The thermal conductivities of the two amorphous silicon films are similar and consistent with the most previous reports with thicknesses no larger than a few μm deposited by a variety of techniques. The thermal conductivities of the three nanocrystalline silicon films are also similar, but are about 50-70% higher than those of their amorphous counterparts. The heat conduction in nanocrystalline silicon films can be understood as the combined contribution in both amorphous and nanocrystalline phases, where increased conduction through improved nanocrystalline percolation path outweighs increased interface scattering between silicon nanocrystals and the amorphous matrix.

Peel-and-stick: mechanism study for efficient fabrication of flexible/transparent thin-film electronics

Peel-and-stick process, or water-assisted transfer printing (WTP), represents an emerging process for transferring fully fabricated thin-film electronic devices with high yield and fidelity from a SiO2/Si wafer to various non-Si based substrates, including papers, plastics and polymers. This study illustrates that the fundamental working principle of the peel-and-stick process is based on the water-assisted subcritical debonding, for which water reduces the critical adhesion energy of metal-SiO2 interface by 70 ~ 80%, leading to clean and high quality transfer of thin-film electronic devices. Water-assisted subcritical debonding is applicable for a range of metal-SiO2 interfaces, enabling the peel-and-stick process as a general and tunable method for fabricating flexible/transparent thin-film electronic devices.

Diffractive light trapping in crystal-silicon films: experiment and electromagnetic modeling

Diffractive light trapping in 1.5 μm thick crystal silicon films is studied experimentally through hemispherical reflection measurements and theoretically through rigorous coupled-wave analysis modeling. The gratings were fabricated by nanoimprinting of dielectric precursor films. The model data, which match the experimental results well without the use of any fitting parameters, are used to extract the light trapping efficiency. Diffractive light trapping is studied as a function of incidence angle, and an enhancement of light absorption is found for incidence angles up to 50° for both TE and TM polarizations.