Fully Integrated Line Array Angular Displacement Sensing Chip

The angular displacement sensor is a digital angular displacement measurement device that integrates optics, mechanics, and electronics. It has important applications in communication, servo control, aerospace, and other fields. Although conventional angular displacement sensors can achieve extremely high measurement accuracy and resolution, they cannot be integrated because complex signal processing circuitry is required at the photoelectric receiver, which limits their suitability for robotics and automotive applications. The design of a fully integrated line array angular displacement-sensing chip is presented for the first time using a combination of pseudo-random and incremental code channel designs. Based on the charge redistribution principle, a fully differential 12-bit, 1 MSPS sampling rate successive approximation analog-to-digital converter (SAR ADC) is designed for quantization and subdivision of the incremental code channel output signal. The design is verified with a 0.35 μm CMOS process and the area of the overall system is 3.5 × 1.8 mm². The fully integrated design of the detector array and readout circuit is realized for the angular displacement sensing.

A Thermopile Detector Based on Micro-Bridges for Heat Transfer

A thermopile detector with their thermocouples distributed in micro-bridges is designed and investigated in this work. The thermopile detector consists of 16 pairs of n-poly-Si/p-poly-Si thermocouples, which are fabricated using a low-cost, high-throughput CMOS process. The micro-bridges are realized by forming micro trenches at the front side first and then releasing the silicon substrate at the back side. Compared with a thermopile device using a continuous membrane, the micro-bridge-based one can achieve an improvement of the output voltage by 13.8% due to a higher temperature difference between the hot and cold junctions as there is a decrease in thermal conduction loss in the partially hollowed structure. This technique provides an effective way for developing high-performance thermopile detectors and other thermal devices.

Manufacturing and Testing of Radio Frequency MEMS Switches Using the Complementary Metal Oxide Semiconductor Process

A radio frequency microelectromechanical system switch (MSS) manufactured by the complementary metal oxide semiconductor (CMOS) process is presented. The MSS is a capacitive shunt type. Structure for the MSS consists of coplanar waveguide (CPW) lines, a membrane, and springs. The membrane locates over the CPW lines. The surface of signal line for the CPW has a silicon dioxide dielectric layer. The fabrication of the MSS contains a CMOS process and a post-process. The MSS has a sacrificial oxide layer after the CMOS process. In the post-processing, a wet etching of buffer oxide etch (BOE) etchant is employed to etch the sacrificial oxide layer, so that the membrane is released. Actuation voltage for the MSS is simulated using the CoventorWare software. The springs have a low stiffness, so that the actuation voltage reduces. The measured results reveal that actuation voltage for the MSS is 10 V. Insertion loss for the MSS is 0.9 dB at 41 GHz and isolation for the MSS is 30 dB at 41 GHz.

Implementation of a fully implantable middle-ear hearing device chip

BACKGROUND AND OBJECTIVE

Recently, with the increase in the population of hearing impaired people, various types of hearing aids have been rapidly developed. In particular, a fully implantable middle ear hearing device (F-IMEHD) is developed for people with sensorineural hearing loss. The F-IMEHD system comprises an implantable microphone, a transducer, and a signal processor. The signal processor should have a small size and consume less power for implantation in a human body.

METHODS

In this study, we designed and fabricated a signal-processing chip using the modified FFT algorithm. This algorithm was developed focusing on eliminating time delay and system complexity in the transform process. The designed signal-processing chip comprises a 4-channel WDRC, a fitting memory, a communication 1control part, and a pulse density modulator. Each channel is separated using a 64-point fast Fourier transform (FFT) method and the gain value is matched using the fitting table in the fitting memory.

RESULTS AND CONCLUSION

The chip was designed by Verilog-HDL and the designed HDL codes were verified by Modelsim-PE 10.3 (Mentor graphics, USA). The chip was fabricated using a 0.18 μm CMOS process (SMIC, China). Experiments were performed on a cadaver to verify the performance of the fabricated chip.

Low-Concentration Ammonia Gas Sensors Manufactured Using the CMOS-MEMS Technique

This study describes the fabrication of an ammonia gas sensor (AGS) using a complementary metal oxide semiconductor (CMOS)–microelectromechanical system (MEMS) technique. The structure of the AGS features interdigitated electrodes (IDEs) and a sensing material on a silicon substrate. The IDEs are the stacked aluminum layers that are made using the CMOS process. The sensing material; polypyrrole/reduced graphene oxide (PPy/RGO), is synthesized using the oxidation–reduction method; and the material is characterized using an electron spectroscope for chemical analysis (ESCA), a scanning electron microscope (SEM), and high-resolution X-ray diffraction (XRD). After the CMOS process; the AGS needs post-processing to etch an oxide layer and to deposit the sensing material. The resistance of the AGS changes when it is exposed to ammonia. A non-inverting amplifier circuit converts the resistance of the AGS into a voltage signal. The AGS operates at room temperature. Experiments show that the AGS response is 4.5% at a concentration of 1 ppm NH₃; and it exhibits good repeatability. The lowest concentration that the AGS can detect is 0.1 ppm NH₃

A Complementary Metal Oxide Semiconductor Process-Compatible Ferroelectric Tunnel Junction

In recent years, experimental demonstration of ferroelectric tunnel junctions (FTJ) based on perovskite tunnel barriers has been reported. However, integrating these perovskite materials into conventional silicon memory technology remains challenging due to their lack of compatibility with the complementary metal oxide semiconductor process (CMOS). This communication reports the fabrication of an FTJ based on a CMOS-compatible tunnel barrier Hf_0.5Zr_0.5O₂ (6 unit cells thick) on an equally CMOS-compatible TiN electrode. Analysis of the FTJ by grazing angle incidence X-ray diffraction confirmed the formation of the noncentrosymmetric orthorhombic phase (Pbc2₁, ferroelectric phase). The FTJ characterization is followed by the reconstruction of the electrostatic potential profile in the as-grown TiN/Hf_0.5Zr_0.5O₂/Pt heterostructure. A direct tunneling current model across a trapezoidal barrier was used to correlate the electronic and electrical properties of our FTJ devices. The good agreement between the experimental and theoretical model attests to the tunneling electroresistance effect (TER) in our FTJ device. A TER ratio of ∼15 was calculated for the present FTJ device at low read voltage (+0.2 V). This study suggests that Hf_0.5Zr_0.5O₂ is a promising candidate for integration into conventional Si memory technology.

Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips

This paper presents an ultra-low embedded power temperature sensor for passive RFID tags. The temperature sensor converts the temperature variation to a PTAT current, which is then transformed into a temperature-controlled frequency. A phase locked loop (PLL)-based sensor interface is employed to directly convert this temperature-controlled frequency into a corresponding digital output without an external reference clock. The fabricated sensor occupies an area of 0.021 mm² using the TSMC 0.18 1P6M mixed-signal CMOS process. Measurement results of the embedded sensor within the tag system shows a 92 nW power dissipation under 1.0 V supply voltage at room temperature, with a sensing resolution of 0.15 °C/LSB and a sensing accuracy of −0.7/0.6 °C from −30 °C to 70 °C after 1-point calibration at 30 °C.

Fabrication and characteristics of an nc-Si/c-Si heterojunction MOSFETs pressure sensor

A novel nc-Si/c-Si heterojunction MOSFETs pressure sensor is proposed in this paper, with four p-MOSFETs with nc-Si/c-Si heterojunction as source and drain. The four p-MOSFETs are designed and fabricated on a square silicon membrane by CMOS process and MEMS technology where channel resistances of the four nc-Si/c-Si heterojunction MOSFETs form a Wheatstone bridge. When the additional pressure is P, the nc-Si/c-Si heterojunction MOSFETs pressure sensor can measure this additional pressure P. The experimental results show that when the supply voltage is 3 V, length-width (L:W) ratio is 2:1, and the silicon membrane thickness is 75 μm, the full scale output voltage of the pressure sensor is 15.50 mV at room temperature, and pressure sensitivity is 0.097 mV/kPa. When the supply voltage and L:W ratio are the same as the above, and the silicon membrane thickness is 45 μm, the full scale output voltage is 43.05 mV, and pressure sensitivity is 2.153 mV/kPa. Therefore, the sensor has higher sensitivity and good temperature characteristics compared to the traditional piezoresistive pressure sensor.