Review of Semiconductor Flash Memory Devices for Material and Process Issues

Vertically integrated NAND (V-NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176-layer-stacked V-NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400-500) due to the total allowable chip thickness, which will be reached within 6-7 years. This review summarizes the current status and critical challenges of charge-trap-based flash memory devices, with a focus on the material (floating-gate vs charge-trap-layer), array-level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell-level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.

A Novel Program Scheme for Z-Interference Improvement in 3D NAND Flash Memory

With gate length (Lg) and gate spacing length (Ls) shrinkage, the cell-to-cell z-interference phenomenon is increasingly severe in 3D NAND charge-trap memory. It has become one of the key reliability concerns for 3D NAND cell scaling. In this work, z-interference mechanisms were investigated in the programming operation with the aid of Technology Computer-Aided Design (TCAD) and silicon data verification. It was found that the inter-cell trapped charges are one of the factors causing z-interference after cell programming, and these trapped charges can be modulated during programming. Thus, a novel program scheme is proposed to suppress the z-interference by reducing the pass voltage (Vpass) of the adjacent cells during programming. As a result, the proposed scheme suppresses the Vth shift of 40.1% for erased cells with Lg/Ls = 31/20 nm. In addition, this work further analyzes the optimization and balance of program disturbance and z-interference with the scaling of cell Lg-Ls based on the proposed scheme.

Fast, Multi-Bit, and Vis-Infrared Broadband Nonvolatile Optoelectronic Memory with MoS2 /2D-Perovskite Van der Waals Heterojunction

Nonvolatile optoelectronic memory (NVOM) integrating the functions of optical sensing and long-term memory can efficiently process and store a large amount of visual scene information, which has become the core requirement of multiple intelligence scenarios. However, realizing NVOM with vis-infrared broadband response is still challenging. Herein, the room temperature vis-infrared broadband NVOM based on few-layer MoS₂ /2D Ruddlesden-Popper perovskite (2D-RPP) van der Waals heterojunction is realized. It is found that the 2D-RPP converts the initial n-type MoS₂ into p-type and facilitates hole transfer between them. Furthermore, the 2D-RPP rich in interband states serves as an effective electron trapping layer as well as broadband photoresponsive layer. As a result, the dielectric-free MoS₂ /2D-RPP heterojunction enables the charge to transfer quickly under external field, which enables a large memory window (104 V), fast write speed of 20 µs, and optical programmable characteristics from visible light (405 nm) to telecommunication wavelengths (i.e., 1550 nm) at room temperature. Trapezoidal optical programming can produce up to 100 recognizable states (>6 bits), with operating energy as low as 5.1 pJ per optical program. These results provide a route to realize fast, low power, multi-bit optoelectronic memory from visible to the infrared wavelength.