DECAL: A Reconfigurable Monolithic Active Pixel Sensor for Tracking and Calorimetry in a 180 nm Image Sensor Process

In this paper, we describe DECAL, a prototype Monolithic Active Pixel Sensor (MAPS) device designed to demonstrate the feasibility of both digital calorimetry and reconfigurability in ASICs for particle physics. The goal of this architecture is to help reduce the development and manufacturing costs of detectors for future colliders by developing a chip that can operate both as a digital silicon calorimeter and a tracking chip. The prototype sensor consists of a matrix of 64 × 64 55 μm pixels, and provides a readout at 40 MHz of the number of particles which have struck the matrix in the preceding 25 ns. It can be configured to report this as a total sum across the sensor (equivalent to the pad of an analogue calorimeter) or the sum per column (equivalent to a traditional strip detector). The design and operation of the sensor are described, and the results of chip characterisation are reported and compared to simulations.

Self-catalyzed InAs nanowires grown on Si: the key role of kinetics on their morphology

Integrating self-catalyzed InAs nanowires on Si(111) is an important step toward building vertical gate-all-around transistors. The complementary metal oxide semiconductor (CMOS) compatibility and the nanowire aspect ratio are two crucial parameters to consider. In this work, we optimize the InAs nanowire morphology by changing the growth mode from Vapor-Solid to Vapor-Liquid-Solid in a CMOS compatible process. We study the key role of the Hydrogen surface preparation on nanowire growths and bound it to a change of the chemical potential and adatoms diffusion length on the substrate. We transfer the optimized process to patterned wafers and adapt both the surface preparation and the growth conditions. Once group III and V fluxes are balances, aspect ratio can be improved by increasing the system kinetics. Overall, we propose a method for large scale integration of CMOS compatible InAs nanowire on silicon and highlight the major role of kinetics on the growth mechanism.

A Study of Optimizing Lamb Wave Acoustic Mass Sensors' Performance through Adjustment of the Transduction Electrode Metallization Ratio

This paper presents the design and simulation of a mass sensitive Lamb wave microsensor with CMOS technology provided by SilTerra. In this work, the effects of the metalization ratio variation on the transmission gain, total harmonic distortion (THD), and two different resonant modes (around 66 MHz and 86 MHz) are shown. It has been found that the metalization ratio can be adjusted in order to obtain a compromise between transmission gain and sensitivity, depending on the design criteria. By adding a Si3N4 layer on top of the device, a five-fold improvement in transmission gain is reached. It was also shown that the transmission of the input differential IDT configuration is 20% more efficient than a single terminal. With this combination, the mass sensitivity is about 114 [cm2/gr].

A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm2. Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode−tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.

A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection

This brief presents an analog front-end (AFE) for the detection of electroencephalogram (EEG) signals. The AFE is composed of four sections, chopper-stabilized amplifiers, ripple suppression circuit, RRAM-based lowpass FIR filter, and 8-bit SAR ADC. This is the first time that an RRAM-based lowpass FIR filter has been introduced in an EEG AFE, where the bio-plausible characteristics of RRAM are utilized to analyze signals in the analog domain with high efficiency. The preamp uses the symmetrical OTA structure, reducing power consumption while meeting gain requirements. The ripple suppression circuit greatly improves noise characteristics and offset voltage. The RRAM-based low-pass filter achieves a 40 Hz cutoff frequency, which is suitable for the analysis of EEG signals. The SAR ADC adopts a segmented capacitor structure, effectively reducing the capacitor switching power consumption. The chip prototype is designed in 40 nm CMOS technology. The overall power consumption is approximately 13 µW, achieving ultra-low-power operation.

Application of Image Sensors to Detect and Locate Electrical Discharges: A Review

Today, there are many attempts to introduce the Internet of Things (IoT) in high-voltage systems, where partial discharges are a focus of concern since they degrade the insulation. The idea is to detect such discharges at a very early stage so that corrective actions can be taken before major damage is produced. Electronic image sensors are traditionally based on charge-coupled devices (CCDs) and, next, on complementary metal oxide semiconductor (CMOS) devices. This paper performs a review and analysis of state-of-the-art image sensors for detecting, locating, and quantifying partial discharges in insulation systems and, in particular, corona discharges since it is an area with an important potential for expansion due to the important consequences of discharges and the complexity of their detection. The paper also discusses the recent progress, as well as the research needs and the challenges to be faced, in applying image sensors in this area. Although many of the cited research works focused on high-voltage applications, partial discharges can also occur in medium- and low-voltage applications. Thus, the potential applications that could potentially benefit from the introduction of image sensors to detect electrical discharges include power substations, buried power cables, overhead power lines, and automotive applications, among others.

An Experimental Investigation of the Degradation of CMOS Low-Noise Amplifier Specifications at Different Temperatures

To investigate the relationship between the specifications degradation of a low-noise amplifier (LNA) and temperature, we experimentally investigated the degradation characteristics of the specifications of the LNA at different temperatures. The small-signal gain (S21) of the LNA decreases with increasing temperature. This paper discusses and analyzes the experimental results in detail, and the reasons for the degradation of LNA specifications with temperature changes are known. Finally, we have tried to use the structure already available in the literature for the PA temperature compensation circuit for the temperature compensation of the LNA. The results show that the existing circuit structure for PA temperature compensation in the literature can also effectively compensate for the S21 and NF degradation of the LNA due to the temperature increase.

Synaptic Segmented Transistor with Improved Linearity by Schottky Junctions and Accelerated Speed by Double-Layered Nitride

Neuromorphic devices have been extensively studied to overcome the limitations of a von Neumann system for artificial intelligence. A synaptic device is one of the most important components in the hardware integration for a neuromorphic system because a number of synaptic devices can be connected to a neuron with compactness as high as possible. Therefore, synaptic devices using silicon-based memory, which are advantageous for a high packing density and mass production due to matured fabrication technologies, have attracted considerable attention. In this study, a segmented transistor devoted to an artificial synapse is proposed for the first time to improve the linearity of the potentiation and depression (P/D). It is a complementary metal oxide semiconductor (CMOS)-compatible device that harnesses both non-ohmic Schottky junctions of the source and drain for improved weight linearity and double-layered nitride for enhanced speed. It shows three distinct and unique segments in drain current-gate voltage transfer characteristics induced by Schottky junctions. In addition, the different stoichiometries of Si_xN_y for a double-layered nitride is utilized as a charge trap layer for boosting the operation speed. This work can bring the industry potentially one step closer to realizing the mass production of hardware-based synaptic devices in the future.

Miniature Wide-Band Noise-Canceling CMOS LNA

In this paper, a wide-band noise-canceling (NC) current conveyor (CC)-based CMOS low-noise amplifier (LNA) is presented. The circuit employs a CC-based approach to obtain wide-band input matching without the need for bulky inductances, allowing broadband performance with a very small area used. The NC technique is applied by subtracting the input transistor’s noise contribution to the output and achieves a noise figure (NF) reduction from 4.8 dB to 3.2 dB. The NC LNA is implemented in a UMC 65-nm CMOS process and occupies an area of only 160 × 80 μm2. It achieves a stable frequency response from 0 to 6.2 GHz, a maximum gain of 15.3 dB, an input return loss (S11) < −10 dB, and a remarkable IIP3 of 7.6 dBm, while consuming 18.6 mW from a ±1.2 V DC supply. Comparisons with similar works prove the effectiveness of this new implementation, showing that the circuit obtains a noteworthy performance trade-off.

Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-In Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-In Self-Repair methods are developed on FPGA, and Verilog’s simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches.

A Fully-Integrated Ambient RF Energy Harvesting System with 423-μW Output Power

This paper proposes a 2.4-GHz fully-integrated single-frequency multi-channel RF energy harvesting (RFEH) system with increased harvested power density. The RFEH can produce an output power of ~423-μW in harvesting ambient RF energy. The front-end consists of an on-chip impedance matching network with a stacked rectifier concurrently matched to a 50 Ω input source. The circuit mitigates the "dead-zone" by enhancing the pumping efficiency, achieved through the increase of V_gs drivability of the proposed internal gate boosting 6-stage low-input voltage charge pump and the 5-stage shared-auxiliary-biasing ring-voltage-controlled-oscillator (VCO) integrated to improve the start-up. The RFEH system, simulated in 180-nm complementary metal-oxide-semiconductor (CMOS), occupies an active area of 1.02 mm². Post-layout simulations show a peak power conversion efficiency(PCE) of 21.15%, driving a 3.3-kΩ load at an input power of 0 dBm and sensitivity of -14.1 dBm corresponding to an output voltage, V_out,RFEH of 1.25 V.

Dual-Step Selective Homoepitaxy of Ge with Low Defect Density and Modulated Strain Based on Optimized Ge/Si Virtual Substrate

In this manuscript, a novel dual-step selective epitaxy growth (SEG) of Ge was proposed to significantly decrease the defect density and to create fully strained relaxed Ge on a Si substrate. With the single-step SEG of Ge, the threading defect density (TDD) was successfully decreased from 2.9 × 10⁷ cm^-2 in a globally grown Ge layer to 3.2 × 10⁵ cm^-2 for a single-step SEG and to 2.84 × 10⁵ cm^-2 for the dual-step SEG of the Ge layer. This means that by introducing a single SEG step, the defect density could be reduced by two orders of magnitude, but this reduction could be further decreased by only 11.3% by introducing the second SEG step. The final root mean square (RMS) of the surface roughness was 0.64 nm. The strain has also been modulated along the cross-section of the sample. Tensile strain appears in the first global Ge layer, compressive strain in the single-step Ge layer and fully strain relaxation in the dual-step Ge layer. The material characterization was locally performed at different points by high resolution transmission electron microscopy, while it was globally performed by high resolution X-ray diffraction and photoluminescence.

A 78.8-84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS

A W-band integer-N phase-locked loop (PLL) for a frequency hopping frequency modulation continuous wave (FMCW) radar is implemented in 65-nm CMOS technology. The cross-coupled voltage-controlled oscillator (VCO) was designed based on a systematic analysis of the VCO combined with its push-pull buffer to achieve high efficiency and high output power. To provide a frequency hopping functionality without any overhead in the implementation, the center frequency of the VCO is steeply controlled by the gate voltage of the buffer, which effectively modifies the susceptance of the VCO load. A stand-alone VCO with the proposed architecture is fabricated, and it achieves an output power of 13.5 dBm, a peak power efficiency of 9.6%, and a tuning range of 3.5%. The phase noise performance of the VCO is −92.6 dBc/Hz at 1-MHz and −106.1 dBc/Hz at 10 MHz offset. Consisting of a third-order loop filter and a divider chain with a total modulus of 48, the locking range of the implemented PLL with the cross-coupled VCO is recorded from 78.84 GHz to 84 GHz, and its phase noise is −85.2 dBc/Hz at 1-MHz offset.

Investigation of the Integration of Strained Ge Channel with Si-Based FinFETs

In this manuscript, the integration of a strained Ge channel with Si-based FinFETs was investigated. The main focus was the preparation of high-aspect-ratio (AR) fin structures, appropriate etching topography and the growth of germanium (Ge) as a channel material with a highly compressive strain. Two etching methods, the wet etching and in situ HCl dry etching methods, were studied to achieve a better etching topography. In addition, the selective epitaxial growth of Ge material was performed on a patterned substrate using reduced pressure chemical vapor deposition. The results show that a V-shaped structure formed at the bottom of the dummy Si-fins using the wet etching method, which is beneficial to the suppression of dislocations. In addition, compressive strain was introduced to the Ge channel after the Ge selective epitaxial growth, which benefits the pMOS transport characteristics. The pattern dependency of the Ge growth over the patterned wafer was measured, and the solutions for uniform epitaxy are discussed.

A 90 GHz Broadband Balanced 8-Way Power Amplifier for High Precision FMCW Radar Sensors in 65-nm CMOS

We present a W-band 8-way wideband power amplifier (PA) for a high precision frequency modulated continuous wave (FMCW) radar in 65-nm CMOS technology. To achieve a broadband operation with an improved output power for a high range resolution and high distance coverage of FMCW radar sensors, a balanced architecture is employed with the Lange coupler which naturally combines the output powers from two 4-way push-pull PAs. By utilizing a transformer-based push-pull structure with a cross-coupled capacitive neutralization technique, the gate-drain capacitance of the 4-way PA is compensated for the stabilization with an improved power gain. Interstage matching was performed with transformers for a reduced loss from the matching network and minimal area occupation. The implemented balanced 8-way PA achieved a saturated output power (P_sat) of 16.5 dBm, a 1-dB compressed output power (OP_1dB) of 13.3 dBm, a power-added efficiency (PAE) of 9.9% at 90 GHz and 3-dB power bandwidth was 20.4 GHz (79.2–99.6 GHz).

Two High-Precision Proximity Capacitance CMOS Image Sensors with Large Format and High Resolution

This paper presents newly developed two high-precision CMOS proximity capacitance image sensors: Chip A with 12 μm pitch pixels with a large detection area of 1.68 cm²; Chip B with 2.8 μm pitch 1.8 M pixels for a higher resolution. Both fabricated chips achieved a capacitance detection precision of less than 100 zF (10⁻¹⁹ F) at an input voltage of 20 V and less than 10 zF (10⁻²⁰ F) at 300 V due to the noise cancelling technique. Furthermore, by using multiple input pulse amplitudes, a capacitance detection dynamic range of up to 123 dB was achieved. The spatial resolution improvement was confirmed by the experimentally obtained modulation transfer function for Chip B with various line and space pattens. The examples of capacitance imaging using the fabricated chips were also demonstrated.

Visible-Band Nanosecond Pulsed Laser Damage Thresholds of Silicon 2D Imaging Arrays

Laser-induced camera damage thresholds were measured for several sensors of three different sensor architectures using a Q-switched Nd:YAG laser in order to determine their pulsed laser-induced damage thresholds. Charge coupled device (CCD), front-side illuminated complimentary metal-oxide semiconductor (FSI CMOS), and back-side illuminated (BSI) CMOS sensors were assessed under laboratory and outdoor environments by increasing the focused laser intensity onto the sensors and recording the sensor output. The damage sites were classified qualitatively into damage types, and pixel counting methods were applied to quantitatively plot damage scale against laser intensity. Probit-fits were applied to find the intensity values where a 95% probability of damage would occur (FD₉₅) and showed that FD₉₅ was approximately the same under laboratory conditions for CCD, FSI CMOS, and BSI CMOS sensors (mean 532 nm FD₉₅ of 0.077 ± 0.01 Jcm^-2). BSI CMOS sensors were the most robust to large-scale damage effects-BSI sensor kill was found at approximately 10³ Jcm^-2, compared to 10 Jcm^-2 for FSI CMOS, and between ~1.6 and 2.7 Jcm^-2 for CCDs.

Strong Radiation Field Online Detection and Monitoring System with Camera

Herein, we report the γ-ray ionizing radiation response of a commercial monolithic active-pixel sensor (MAPS) camera under strong-dose-rate irradiation with an online detection and monitoring system for strong radiation conditions. We present the first results of the distribution of three types of MAPS camera and establish a linear relationship between the average response signal and radiation dose rate in the strong-dose-rate range. There is an obvious response signal in the video frames when the camera module parameters are set to automatic, but the linear response is very poor. However, the fixed image parameters are not good at adapting to the changes of the environment and affect the quality of the video frames. A dual module online radiation detection and monitoring probe was made to carry out effective video monitoring and radiation detection at the same time. The measurement results show that the dose rate detection error is less than 5% with a dose rate in the range of 60 to 425 Gy/h, and the visible light image does not have obvious distortion, deformation, or color shift due to the interference of the radiation response event and radiation damage. Hence, the system test results show that it can be used for online detection and monitoring in a strong radiation environment.

High-Performance Carbon Nanotube-Based Transient Complementary Electronics

Transient electronics is an emerging class of electronic devices that can physically degrade or disintegrate after a stable period of service, showing a vast prospect in applications of "green" consumer electronics, hardware-secure devices, medical implants, etc. Complementary metal-oxide-semiconductor (CMOS) technology is dominant in integrated circuit design for its advantages of low static power consumption, high noise immunity, and simple design layout, which also work and are highly preferred for transient electronics. However, the performance of complementary transient electronics is severely restricted by the confined selection of transient materials and compatible fabrication strategies. Here, we report the realization of high-performance transient complementary electronics based on carbon nanotube thin films via a reliable electrostatic doping method. Under a low operating voltage of 2 V, on a 1.5 μm-thick water-soluble substrate made of poly(vinyl alcohol), the width-normalized on-state currents of the p-type and n-type transient thin-film transistors (TFTs) reach 4.5 and 4.7 μA/μm, and the width-normalized transconductances reach 2.8 and 3.7 μS/μm, respectively. Meanwhile, these TFTs show small subthreshold swings no more than 108 mV/dec and current on/off ratios above 10⁶ with good uniformity. Transient CMOS inverters, as basic circuit components, are demonstrated with a voltage gain of 24 and a high noise immunity of 67.4%. Finally, both the degradation of the active components and the disintegration of the functional system are continuously monitored with nontraceable remains after 10 and 5 h, respectively.

Single-shot experiments at the soft X-FEL FERMI using a back-side-illuminated scientific CMOS detector. Corrigendum

The name of one of the authors in the article by Léveillé et al. [(2022), J. Synchrotron Rad. 29, 103-110] is corrected.

Engineered Biological Neural Networks on High Density CMOS Microelectrode Arrays

In bottom-up neuroscience, questions on neural information processing are addressed by engineering small but reproducible biological neural networks of defined network topology in vitro. The network topology can be controlled by culturing neurons within polydimethylsiloxane (PDMS) microstructures that are combined with microelectrode arrays (MEAs) for electric access to the network. However, currently used glass MEAs are limited to 256 electrodes and pose a limitation to the spatial resolution as well as the design of more complex microstructures. The use of high density complementary metal-oxide-semiconductor (CMOS) MEAs greatly increases the spatial resolution, enabling sub-cellular readout and stimulation of neurons in defined neural networks. Unfortunately, the non-planar surface of CMOS MEAs complicates the attachment of PDMS microstructures. To overcome the problem of axons escaping the microstructures through the ridges of the CMOS MEA, we stamp-transferred a thin film of hexane-diluted PDMS onto the array such that the PDMS filled the ridges at the contact surface of the microstructures without clogging the axon guidance channels. This method resulted in 23 % of structurally fully connected but sealed networks on the CMOS MEA of which about 45 % showed spiking activity in all channels. Moreover, we provide an impedance-based method to visualize the exact location of the microstructures on the MEA and show that our method can confine axonal growth within the PDMS microstructures. Finally, the high spatial resolution of the CMOS MEA enabled us to show that action potentials follow the unidirectional topology of our circular multi-node microstructure.

NMR spectroscopy of a single mammalian early stage embryo

The resolving power, chemical sensitivity and non-invasive nature of NMR have made it an established technique for in vivo studies of large organisms both for research and clinical applications. NMR would clearly be beneficial for analysis of entities at the microscopic scale of about 1 nL (the nanoliter scale), typical of early development of mammalian embryos, microtissues and organoids: the scale where the building blocks of complex organisms could be observed. However, the handling of such small samples (about 100 µm) and sensitivity issues have prevented a widespread adoption of NMR. In this article we show how these limitations can be overcome to obtain NMR spectra of a mammalian embryo in its early stage. To achieve this we employ ultra-compact micro-chip technologies in combination with 3D-printed micro-structures. Such device is packaged for use as plug & play sensor and it shows sufficient sensitivity to resolve NMR signals from individual bovine pre-implantation embryos. The embryos in this study are obtained through In Vitro Fertilization (IVF) techniques, transported cryopreserved to the NMR laboratory, and measured shortly after thawing. In less than 1 h these spherical samples of just 130-190 µm produce distinct spectral peaks, largely originating from lipids contained inside them. We further observe how the spectra vary from one sample to another despite their optical and morphological similarities, suggesting that the method can further develop into a non-invasive embryo assay for selection prior to embryo transfer.

Modular head-mounted cortical imaging device for chronic monitoring of intrinsic signals in mice

SIGNIFICANCE

Intrinsic optical signals (IOS) generated in the cortical tissue as a result of various interacting metabolic processes are used extensively to elucidate the underlying mechanisms that govern neurovascular coupling. However, current IOS measurements still often rely on bulky, tabletop imaging systems, and there remains a dearth of studies in freely moving subjects. Lightweight, miniature head-mounted imaging devices provide unique opportunities for investigating cortical dynamics in small animals under a variety of naturalistic behavioral settings.

AIM

The aim of this work was to monitor IOS in the somatosensory cortex of wild-type mice by developing a lightweight, biocompatible imaging device that readily lends itself to animal experiments in freely moving conditions.

APPROACH

Herein we describe a method for realizing long-term IOS imaging in mice using a 0.54-g, compact, CMOS-based, head-mounted imager. The two-part module, consisting of a tethered sensor plate and a base plate, allows facile assembly prior to imaging sessions and disassembly when the sensor is not in use. LEDs integrated into the device were chosen to illuminate the cortical mantle at two different wavelengths in the visible regime (λcenter: 535 and 625 nm) for monitoring volume- and oxygenation state-dependent changes in the IOS, respectively. To test whether the system can detect robust cortical responses, we recorded sensory-evoked IOS from mechanical stimulation of the hindlimbs (HL) of anesthetized mice in both acute and long-term implantation conditions.

RESULTS

Cortical IOS recordings in the primary somatosensory cortex hindlimb receptive field (S1HL) of anesthetized mice under green and red LED illumination revealed robust, multiphasic profiles that were time-locked to the mechanical stimulation of the contralateral plantar hindpaw. Similar intrinsic signal profiles observed in S1HL at 40 days postimplantation demonstrated the viability of the approach for long-term imaging. Immunohistochemical analysis showed that the brain tissue did not exhibit appreciable immune response due to the device implantation and operation. A proof-of-principle imaging session in a freely behaving mouse showed minimal locomotor impediment for the animal and also enabled estimation of blood flow speed.

CONCLUSIONS

We demonstrate the utility of a miniature cortical imaging device for monitoring IOS and related hemodynamic processes in both anesthetized and freely moving mice, cueing potential for applications to some neuroscientific studies of sensation and naturalistic behavior.

Embedded UV Sensors in CMOS SOI Technology

We report on ultraviolet (UV) sensors employing high voltage PIN lateral photodiode strings integrated into the production RF SOI (silicon on isolator) CMOS platform. The sensors were optimized for applications that require measurements of short wavelength ultraviolet (UVC) radiation under strong visible and near-infrared lights, such as UV used for sterilization purposes, e.g., COVID-19 disinfection. Responsivity above 0.1 A/W in the UVC range was achieved, and improved blindness to visible and infrared (IR) light demonstrated by implementing back-end dielectric layers transparent to the UV, in combination with differential sensing circuits with polysilicon UV filters. Degradation of the developed sensors under short wavelength UV was investigated and design and operation regimes allowing decreased degradation were discussed. Compared with other embedded solutions, the current design is implemented in a mass-production CMOS SOI technology, without additional masks, and has high sensitivity in UVC.

Multipurpose Bio-Monitored Integrated Circuit in a Contact Lens Eye-Tracker

We present the design, fabrication, and test of a multipurpose integrated circuit (Application Specific Integrated Circuit) in AMS 0.35 µm Complementary Metal Oxide Semiconductor technology. This circuit is embedded in a scleral contact lens, combined with photodiodes enabling the gaze direction detection when illuminated and wirelessly powered by an eyewear. The gaze direction is determined by means of a centroid computation from the measured photocurrents. The ASIC is used simultaneously to detect specific eye blinking sequences to validate target designations, for instance. Experimental measurements and validation are performed on a scleral contact lens prototype integrating four infrared photodiodes, mounted on a mock-up eyeball, and combined with an artificial eyelid. The eye-tracker has an accuracy of 0.2°, i.e., 2.5 times better than current mobile video-based eye-trackers, and is robust with respect to process variations, operating time, and supply voltage. Variations of the computed gaze direction transmitted to the eyewear, when the eyelid moves, are detected and can be interpreted as commands based on blink duration or using blinks alternation on both eyes.