Limitations and Drawbacks of DQE Estimation Methods Applied to Electron Detectors

The DQE is generally accepted as the main figure of merit for the comparison between electron detectors, and most of the time given as a unique number at the Nyquist frequency while it is known to vary with electron dose. It is usually estimated thanks to a method improved by McMullan in 2009. The purpose of this work is to analyse and to criticize this DQE extraction method on the basis of measurement and model results, and to give recommendations for fair comparison between detectors, wondering if the DQE is the right figure of merit for electron detectors.

New structure transistors for advanced technology node CMOS ICs

Over recent decades, advancements in complementary metal-oxide-semiconductor integrated circuits (ICs) have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor (FinFET) and gate-all-around FET (GAAFET), more gate electrodes have been added to three-dimensional (3D) channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore's law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g. in complementary FETs (CFET), 3D stack (3DS) FETs and vertical-channel transistors (VFET), for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

Fully Integrated 24-GHz 1TX-2RX Transceiver for Compact FMCW Radar Applications

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is -80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm2 die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets.

Enhancement-Mode Ambipolar Thin-Film Transistors and CMOS Logic Circuits using Bilayer Ga2O3/NiO Semiconductors

Recent advancements in power electronics have been driven by Ga2O3-based ultrawide bandgap (UWBG) semiconductor devices, enabling efficient high-current switching. However, integrating Ga2O3 power devices with essential silicon CMOS logic circuits for advanced control poses fabrication challenges. Researchers have introduced Ga2O3-based NMOS and pseudo-CMOS circuits for integration, but these circuits may either consume more power or increase the design complexity. Hence, this article proposes Ga2O3-based CMOS realized using heterogeneous 3D-stacked bilayer ambipolar transistors. These ambipolar transistors consist of HfO2/NiO/Ga2O3/NiO/HfO2 heterostructures that are wrapped around by the Ti/Au gate electrode, resulting in record high electron and hole current on/off ratios of 109 and 107. The threshold voltage, subthreshold swing, and current density measured from 100 ambipolar devices (across 5 batches) are around -7.99 ± 0.92 V (p-channel) and 7.81 ± 0.81 V (n-channel), 0.59 ± 0.07 V/dec (p-channel) and 0.61 ± 0.06 V/dec (n-channel), and 0.99 ± 0.26 mA/mm (p-channel) and 58.23 ± 12.99 mA/mm (n-channel), respectively. All the 100 ambipolar devices showed decent long-term stability over a period of 200 days, exhibiting reliable electrical performance. The threshold voltage shift (ΔVTH) after negative bias stressing for a period of 3500 s is around 11.52 V (p-channel) and 10.21 V (n-channel), respectively. Notably, the n-channels exhibit ∼2 orders higher on/off ratio than the best Ga2O3 unipolar transistors at 300 °C. Moreover, the polarities of ambipolar transistors are reconfigurable into p- or n-MOS, which are integrated to demonstrate CMOS inverter, NOR, and NAND logic gates. The switching periods from "0" to "1" and from "1" to "0" of NOR are 0.12 and 0.17 μs, and those of NAND are 0.16 and 0.13 μs. This work lays the foundation of oxide-semiconductor-based CMOS for future integrated electronics.

Investigation and Modeling of the Behavior of Temperature Characteristics of 0.3-1.1 GHz Complementary Metal Oxide Semiconductor Class-A Broadband Power Amplifiers

A power amplifier (PA) stands as a central module within the electronic information system (EIS), and any variation in a PA's specifications has a direct impact on the EIS's performance, especially in the face of temperature fluctuations. In examining the influence of PA specification changes on the EIS, we employed support vector machine (SVM) to model the behavior of the temperature characteristics of 0.3-1.1 GHz complementary metal oxide semiconductor (CMOS) class-A broadband PAs. The results show that the parameters of S11, S12, S21, and S22 can be effectively modeled. SVM outperforms Elman and GRNN in terms of combined modeling time and modeling accuracy. This research can be extended to modeling the behavior of other types of power amplifiers or devices and circuits.

A Multidisciplinary Approach toward CMOS Capacitive Sensor Array for Droplet Analysis

This paper introduces an innovative method for the analysis of alcohol-water droplets on a CMOS capacitive sensor, leveraging the controlled thermal behavior of the droplets. Using this sensing method, the capacitive sensor measures the total time of evaporation (ToE), which can be influenced by the droplet volume, temperature, and chemical composition. We explored this sensing method by introducing binary mixtures of water and ethanol or methanol across a range of concentrations (0-100%, with 10% increments). The experimental results indicate that while the capacitive sensor is effective in measuring both the total ToE and dielectric properties, a higher dynamic range and resolution are observed in the former. Additionally, an array of sensing electrodes successfully monitors the droplet-sensor surface interaction. However practical considerations such as the creation of parasitic capacitance due to mismatch, arise from the large sensing area in the proposed capacitive sensors and other similar devices. In this paper, we discuss this non-ideality and propose a solution. Also, this paper showcases the benefits of utilizing a CMOS capacitive sensing method for accurately measuring ToE.

A Dual-Mode CMOS Power Amplifier with an External Power Amplifier Driver Using 40 nm CMOS for Narrowband Internet-of-Things Applications

The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying -45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications.

Preliminary Characterization of an Active CMOS Pad Detector for Tracking and Dosimetry in HDR Brachytherapy

We assessed the accuracy of a prototype radiation detector with a built in CMOS amplifier for use in dosimetry for high dose rate brachytherapy. The detectors were fabricated on two substrates of epitaxial high resistivity silicon. The radiation detection performance of prototypes has been tested by ion beam induced charge (IBIC) microscopy using a 5.5 MeV alpha particle microbeam. We also carried out the HDR Ir-192 radiation source tracking at different depths and angular dose dependence in a water equivalent phantom. The detectors show sensitivities spanning from (5.8 ± 0.021) × 10-8 to (3.6 ± 0.14) × 10-8 nC Gy-1 mCi-1 mm-2. The depth variation of the dose is within 5% with that calculated by TG-43. Higher discrepancies are recorded for 2 mm and 7 mm depths due to the scattering of secondary particles and the perturbation of the radiation field induced in the ceramic/golden package. Dwell positions and dwell time are reconstructed within ±1 mm and 20 ms, respectively. The prototype detectors provide an unprecedented sensitivity thanks to its monolithic amplification stage. Future investigation of this technology will include the optimisation of the packaging technique.

High-resolution X-Ray imaging of small animal samples based on Commercial-Off-The-Shelf CMOS image sensors

 An automated system for acquiring microscopic-resolution radiographic images of biological samples was developed. Mass-produced, low-cost, and easily automated components were used, such as Commercial-Off-The-Self CMOS image sensors (CIS), stepper motors, and control boards based on Arduino and RaspberryPi. System configuration, imaging protocols, and Image processing (filtering and stitching) were defined to obtain high-resolution images and for successful computational image reconstruction. Radiographic images were obtained for animal samples including the widely used animal models zebrafish (Danio rerio) and the fruit-fly (Drosophila melanogaster), as well as other small animal samples. The use of phosphotungstic acid (PTA) as a contrast agent was also studied. Radiographic images with resolutions of up to (7±0.6)μm were obtained, making this system comparable to commercial ones. This work constitutes a starting point for the development of more complex systems such as X-ray attenuation micro-tomography systems based on low-cost off-the-shelf technology. It will also bring the possibility to expand the studies that can be carried out with small animal models at many institutions (mostly those working on tight budgets), particularly those on the effects of ionizing radiation and absorption of heavy metal contaminants in animal tissues.

Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications

A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including nine SPADs using 0.18 µm high-voltage CMOS technology. The gating circuit achieves rise and fall times of 480 ps and 280 ps, respectively, and a minimum full-width-at-half-maximum pulse width of 1.26 ns. Thanks to a fast and sensitive comparator, a detection threshold for avalanche events of less than 100 mV is possible. The power consumption of all nine channels is about 250 mW in total. This gating chip is used to characterize the integrated SPADs. A photon detection probability of around 50% at 9.9 V excess bias and for a wavelength of 635 nm is found.

Single-Grating Monolithic Spatial Heterodyne Raman Spectrometer: An Investigation on the Effects of Detector Selection

Spatial heterodyne Raman spectrometers (SHRSs) are modified forms of Michelson interferometers, except the mirrors in a Michelson interferometer are replaced with stationary diffraction gratings. This design removes the need for an entrance slit, as is the case in a dispersive spectrometer, and removes the need to scan the spectrum by using a moving mirror in a modern Michelson interferometer. In previous studies, various SHRS variants, such as free-standing two-grating SHRS, single-grating SHRS (1g-SHRS), monolithic SHRS (mSHRS), and single-grating mSHRS (1g-mSHRS), have been evaluated. However, the present study exclusively focuses on the 1g-mSHRS configuration. The 1g-mSHRS and 1g-SHRS increase the spectral range at fixed grating line density while trading off spectral resolution and resolving power. The mSHRS benefits from increased rigidity, lack of moving parts, and reduced footprint. In this study, we investigate how the choice of detector impacts the performance of the 1g-mSHRS system, with a specific focus on evaluating the performance of three types of cameras: charged-coupled device (CCD), intensified CCD (ICCD), and complementary metal-oxide-semiconductor (CMOS) cameras. These systems were evaluated using geological, organic, and inorganic samples using a 532 nm continuous wave laser for the CMOS and CCD cameras, and a 532 nm neodymium-doped yttrium aluminum garnet pulsed laser for the ICCD camera. The footprint of the 1g-mSHRS was 3.5 × 3.5 × 2.5 cm3 with a mass of 272 g or 80 g, depending on whether the monolith housing is included or not. We found that increasing the number of pixels utilized along the x-axis of the camera increases fringe visibility (FV) and optimizes the resolution (by capturing the entirety of the grating and magnifying the fringes). The number of pixels utilized in the y-axis, chip size, and dimensions, affect the signal-to-noise ratio of the systems. Additionally, we discuss the effect of pixel pitch on the recovery of Fizeau fringes, including the relationship between the Nyquist frequency, aliasing, and FV.

High-Performance Complementary Circuits from Two-Dimensional MoTe2

Two-dimensional (2D) materials hold great promise for future complementary metal-oxide semiconductor (CMOS) technology. However, the lack of effective methods to tune the Schottky barrier poses a challenge in constructing high-performance complementary circuits from the same material. Here, we reveal that the polarity of pristine MoTe2 field-effect transistors (FETs) with minimized air exposure is n-type, irrespective of the metal contact type. The fabricated n-FETs with palladium contact can reach electron currents up to 275 μA/μm at VDS = 2 V. For p-FETs, we introduce a novel nitric oxide doping strategy, allowing a controlled transition of MoTe2 FETs from n-type to unipolar p-type. By doping only in the contact region, we demonstrate hole currents up to 170 μA/μm at VDS= -2 V with preserved Ion/Ioff ratios of 105. Finally, we present a complementary inverter circuit comprising the high-performance n- and p-type FETs based on MoTe2, promoting the application of 2D materials in future electronic systems.

Metal Microelectromechanical Resonator Exhibiting Fast Human Activity Detection

This work presents a MEMS resonator used as an ultra-high resolution water vapor sensor (humidity sensing) to detect human activity through finger movement as a demonstrator example. This microelectromechanical resonator is designed as a clamped-clamped beam fabricated using the top metal layer of a commercial CMOS technology (0.35 μm CMOS-AMS) and monolithically integrated with conditioning and readout circuitry. Sensing is performed through the resonance frequency change due to the addition of water onto the clamped-clamped beam coming from the moisture created by the evaporation of water in the human body. The sensitivity and high-speed response to the addition of water onto the metal bridge, as well as the quick dewetting of the surface, make it suitable for low-power human activity sensing.

A Synthetic Ultra-Wideband Transceiver for Millimeter-Wave Imaging Applications

In this work, we present a transceiver front-end in SiGe BiCMOS technology that can provide an ultra-wide bandwidth of 100 GHz at millimeter-wave frequencies. The front-end utilizes an innovative arrangement to efficiently distribute broadband-generated pulses and coherently combine received pulses with minimal loss. This leads to the realization of a fully integrated ultra-high-resolution imaging chip for biomedical applications. We realized an ultra-wide imaging band-width of 100 GHz via the integration of two adjacent disjointed frequency sub-bands of 10-50 GHz and 50-110 GHz. The transceiver front-end is capable of both transmit (TX) and receive (RX) operations. This is a crucial component for a system that can be expanded by repeating a single unit cell in both the horizontal and vertical directions. The imaging elements were designed and fabricated in Global Foundry 130-nm SiGe 8XP process technology.

Fabrication and Characterization of Photovoltaic Microgenerators Using the Complementary Metal Oxide Semiconductor Process

This study develops a photovoltaic microgenerator based on the complementary metal oxide semiconductor (CMOS) process. The photovoltaic microgenerator converts the absorbed light energy into electrical energy using the photovoltaic effect. The material for the photovoltaic microgenerator is silicon, and its structure consists of patterned p-n junctions. The design of the photovoltaic microgenerator utilizes a grid-like shape, forming a large-area p-n junction with a patterned p-doping and N-well structure to enhance the photocurrent and improve the device's performance. The photovoltaic microgenerator is fabricated employing the CMOS process with post-processing step. Post-processing is applied to enhance the microgenerator's light absorption and energy-conversion efficiency. This involves using wet etching with buffered-oxide etch (BOE) to remove the silicon dioxide layer above the p-n junctions, allowing direct illumination of the p-n junctions. The area of the photovoltaic microgenerator is 0.79 mm2. The experimental results show that under an illumination intensity of 1000 W/m2, the photovoltaic microgenerator exhibits an open-circuit voltage of 0.53 V, a short-circuit current of 233 µA, a maximum output power of 99 µW, a fill factor of 0.8, and an energy-conversion efficiency of 12.5%.

Microscale 3-D Capacitance Tomography with a CMOS Sensor Array

Electrical capacitance tomography (ECT) is a non-optical imaging technique in which a map of the interior permittivity of a volume is estimated by making capacitance measurements at its boundary and solving an inverse problem. While previous ECT demonstrations have often been at centimeter scales, ECT is not limited to macroscopic systems. In this paper, we demonstrate ECT imaging of polymer microspheres and bacterial biofilms using a CMOS microelectrode array, achieving spatial resolution of 10 microns. Additionally, we propose a deep learning architecture and an improved multi-objective training scheme for reconstructing out-of-plane permittivity maps from the sensor measurements. Experimental results show that the proposed approach is able to resolve microscopic 3-D structures, achieving 91.5% prediction accuracy on the microsphere dataset and 82.7% on the biofilm dataset, including an average of 4.6% improvement over baseline computational methods.

A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques

Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area. It includes a single-ended differential feedback operational transconductance amplifier (OTA) and n-pass MUX-based AFE circuits which are related to the emergence of low power, low area, and low cost AFE-integrated chips that are required for wearable biomedical applications. The proposed 6T n-pass multiplexer measures a gain of -68 dB across a frequency range of 100 kHz with a 136.5 nW power consumption and a delay of 0.07 ns. The design layout area is approximately 9.8 µm2 and uses 45 nm complementary metal oxide semiconductor (CMOS) technology. Additionally, the proposed single-ended differential OTA has an obtained input referred noise of 0.014 µVrms, and a gain of -5.5 dB, while the design layout area is about 2 µm2 and was designed with the help of the Cadence Virtuoso layout design tool.

A 54 µW CMOS Auto-Trimming Bandgap References (ATBGR) Achieving 90 dB PSRR for Artificial Intelligence of Things (AIoT) Chips

An Auto-Trimming CMOS Bandgap References Circuit (ATBGR) with PSRR enhancement circuit for Artificial Intelligence of Things (AIoT) chips is presented in this paper. The ATBGR is designed with a first-order temperature compensation technique providing a stable reference voltage of 1.25 V in the ranges of input voltages from 1.65 V to 4.5 V. An auto-trimming circuit is integrated into a PTAT resistor of BGR to minimize the influences of the process variations. The four parallel resistor pairs with PMOS switches are connected in series with the PTAT resistor. The reference voltage, VREF, is compared to an external constant value, 1.25 V, through an operational amplifier, and the output of the de-multiplexer is used to configure the PMOS switches. High power supply rejection is achieved through a PSRR enhancement circuit constituting a cascaded PMOS common gate pair. The ATBGR circuit is fabricated in 180 nm CMOS technology, consuming an area of 0.03277 mm2. The auto-trimming method yields an average temperature coefficient of 9.99 ppm/°C with temperature ranges from -40 °C to 125 °C, and a power supply rejection ratio of -90 dB at 100 MHz is obtained. The line regulation of the proposed circuit is 0.434%/V with power consumption of 54.12 µW at room temperature.

"GeSn Rule-23"-The Performance Limit of GeSn Infrared Photodiodes

Group-IV GeSn photodetectors (PDs) compatible with standard complementary metal-oxide-semiconductor (CMOS) processing have emerged as a new and non-toxic infrared detection technology to enable a wide range of infrared applications. The performance of GeSn PDs is highly dependent on the Sn composition and operation temperature. Here, we develop theoretical models to establish a simple rule of thumb, namely "GeSn-rule 23", to describe GeSn PDs' dark current density in terms of operation temperature, cutoff wavelength, and Sn composition. In addition, analysis of GeSn PDs' performance shows that the responsivity, detectivity, and bandwidth are highly dependent on operation temperature. This rule provides a simple and convenient indicator for device developers to estimate the device performance at various conditions for practical applications.

A State-of-the-Art Review on CMOS Radio Frequency Power Amplifiers for Wireless Communication Systems

Wireless communication systems have undergone significant development in recent years, particularly with the transition from fourth generation (4G) to fifth generation (5G). As the number of wireless devices and mobile data usage increase, there is a growing need for enhancements and upgrades to the current wireless communication systems. CMOS transceivers are increasingly being explored to meet the requirements of the latest wireless communication protocols and applications while achieving the goal of system-on-chip (SoC). The radio frequency power amplifier (RFPA) in a CMOS transmitter plays a crucial role in amplifying RF signals and transmitting them from the antenna. This state-of-the-art review paper presents a concise discussion of the performance metrics that are important for designing a CMOS PA, followed by an overview of the trending research on CMOS PA techniques that focuses on efficiency, linearity, and bandwidth enhancement.

An Ultra-Low-Power Analog Multiplier-Divider Compatible with Digital Code for RRAM-Based Computing-in-Memory Macros

This manuscript presents an ultra-low-power analog multiplier-divider compatible with digital code words, which is applicable to the integrated structure of resistive random-access memory (RRAM)-based computing-in-memory (CIM) macros. Current multiplication and division are accomplished by a current-mirror-based structure. Compared with digital dividers to achieve higher precision and operation speed, analog dividers present the advantages of a reduced power consumption and a simple circuit structure in lower precision operations, thus improving the energy efficiency. Designed and fabricated in a 55 nm CMOS process, the proposed work is capable of achieving 8-bit precision for analog current multiplication and division operations. Measurement results show that the signal delay is 1 μs when performing 8-bit operation, with a bandwidth of 1.4 MHz. The power consumption is less than 6.15 μW with a 1.2 V supply voltage. The proposed multiplier-divider can increase the operation capacity by dividing the input current and digital code while reducing the power consumption and complexity required by division, which can be further utilized in real-time operation of edge computing devices.

A Compact and Low-Power SoC Design for Spiking Neural Network Based on Current Multiplier Charge Injector Synapse

This paper presents a compact analog system-on-chip (SoC) implementation of a spiking neural network (SNN) for low-power Internet of Things (IoT) applications. The low-power implementation of an SNN SoC requires the optimization of not only the SNN model but also the architecture and circuit designs. In this work, the SNN has been constituted from the analog neuron and synaptic circuits, which are designed to optimize both the chip area and power consumption. The proposed synapse circuit is based on a current multiplier charge injector (CMCI) circuit, which can significantly reduce power consumption and chip area compared with the previous work while allowing for design scalability for higher resolutions. The proposed neuron circuit employs an asynchronous structure, which makes it highly sensitive to input synaptic currents and enables it to achieve higher energy efficiency. To compare the performance of the proposed SoC in its area and power consumption, we implemented a digital SoC for the same SNN model in FPGA. The proposed SNN chip, when trained using the MNIST dataset, achieves a classification accuracy of 96.56%. The presented SNN chip has been implemented using a 65 nm CMOS process for fabrication. The entire chip occupies 0.96 mm2 and consumes an average power of 530 μW, which is 200 times lower than its digital counterpart.

A Multimode 28 GHz CMOS Fully Differential Beamforming IC for Phased Array Transceivers

A 28 GHz fully differential eight-channel beamforming IC (BFIC) with multimode operations is implemented in 65 nm CMOS technology for use in phased array transceivers. The BFIC has an adjustable gain and phase control on each channel to achieve fine beam steering and beam pattern. The BFIC has eight differential beamforming channels each consisting of the two-stage bi-directional amplifier with a precise gain control circuit, a six-bit phase shifter, a three-bit digital step attenuator, and a tuning bit for amplitude and phase variation compensation. The Tx and Rx mode overall gains of the differential eight-channel BFIC are around 11 dB and 9 dB, respectively, at 27.0-29.5 GHz. The return losses of the Tx mode and Rx mode are >10 dB at 27.0-29.5 GHz. The maximum phase of 354° with a phase resolution of 5.6° and the maximum attenuation of 31 dB, including the gain control bits with an attenuation resolution of 1 dB, is achieved at 27.0-29.5 GHz. The root mean square (RMS) phase and amplitude errors are <3.2° and <0.6 dB at 27.0-29.5 GHz, respectively. The chip size is 3.0 × 3.5 mm², including pads, and Tx mode current consumption is 580 mA at 2.5 V supply voltage.

Exploring the Potential of Broadband Complementary Metal Oxide Semiconductor Micro-Coil Nuclear Magnetic Resonance for Environmental Research

With sensitivity being the Achilles' heel of nuclear magnetic resonance (NMR), the superior mass sensitivity offered by micro-coils can be an excellent choice for tiny, mass limited samples such as eggs and small organisms. Recently, complementary metal oxide semiconductor (CMOS)-based micro-coil transceivers have been reported and demonstrate excellent mass sensitivity. However, the ability of broadband CMOS micro-coils to study heteronuclei has yet to be investigated, and here their potential is explored within the lens of environmental research. Eleven nuclei including 7Li, 19F, 31P and, 205Tl were studied and detection limits in the low to mid picomole range were found for an extended experiment. Further, two environmentally relevant samples (a sprouting broccoli seed and a D. magna egg) were successfully studied using the CMOS micro-coil system. 13C NMR was used to help resolve broad signals in the 1H spectrum of the 13C enriched broccoli seed, and steady state free precession was used to improve the signal-to-noise ratio by a factor of six. 19F NMR was used to track fluorinated contaminants in a single D. magna egg, showing potential for studying egg-pollutant interactions. Overall, CMOS micro-coil NMR demonstrates significant promise in environmental research, especially when the future potential to scale to multiple coil arrays (greatly improving throughput) is considered.

A Low-Cost Measurement Methodology for LiDAR Receiver Integrated Circuits

This paper presents a test methodology to facilitate the measuring processes of LiDAR receiver ICs by avoiding the inherent walk error issue. In a typical LiDAR system, a costly laser diode driver emits narrow light pulses with fast rising edges, and the reflected pulses from targets enter an optical detector followed by an analog front-end (AFE) circuit. Then, the received signals pass through the cascaded amplifiers down to the time-to-digital converter (TDC) that can estimate the detection range. However, this relatively long signal journey leads to the significant decline of rising-edge slopes and the output pulse spreading, thus producing inherent walk errors in LiDAR receiver ICs. Compensation methods requiring complex algorithms and extra chip area have frequently been exploited to lessen the walk errors. In this paper, however, a simpler and lower-cost methodology is proposed to test LiDAR receiver ICs by employing a high-speed buffer and variable delay cells right before the TDC. With these circuits, both START and STOP pulses show very similar pulse shapes, thus effectively avoiding the walk error issue. Additionally, the time interval between two pulses is easily determined by varying the number of the delay cells. Test chips of the proposed receiver IC implemented in a 180-nm CMOS process successfully demonstrate easier and more accurate measurement results.

A Route toward High-Detectivity and Low-Cost Short-Wave Infrared Photodetection: GeSn/Ge Multiple-Quantum-Well Photodetectors with a Dielectric Nanohole Array Metasurface

High-detectivity and low-cost short-wave infrared photodetectors with complementary metal-oxide-semiconductor (CMOS) compatibility are attractive for various applications such as next-generation optical communication, LiDAR, and molecular sensing. Here, GeSn/Ge multiple-quantum-well (MQW) photodetectors with a dielectric nanohole array metasurface were proposed to realize high-detectivity and low-cost SWIR photodetection. The Ge nanohole array metasurface was utilized to enhance the light absorption in the GeSn/Ge MQW active layer. Compared with metallic nanostructures, the dielectric nanohole structure has the advantages of low intrinsic loss and CMOS compatibility. The introduction of metasurface architecture facilitates a 10.5 times enhanced responsivity of 0.232 A/W at 2 μm wavelength while slightly sacrificing the dark current density. Besides, the metasurface GeSn/Ge MQW photodetectors benefit 35% improvement in the 3 dB bandwidth compared to control GeSn/Ge MQW photodetectors, which can be attributed to the reduced RC delay. Due to the high responsivity and low dark current density, the room temperature specific detectivity at 2 μm is as high as 5.34 × 10⁹ cm·Hz^1/2/W, which is the highest among GeSn photodetectors and is better than commercial InSb and PbSe photodetectors operating at the similar wavelength. This work offers a promising approach for achieving low-cost and effective photodetection at 2 μm, contributing to the development of the 2 μm communication band.

CMOS compatible 2T pixel for on-wafer in-situ EUV detection

A novel 2-transistor (2T) pixel EUV detector is proposed and demonstrated by advanced CMOS technology. The proposed 2T detector also exhibits high spectral range (< 267 nm) and spatial resolution (67 μm) with high stability and CMOS Compatibility. The compact 2T EUV detector pixels arranged in a test array are capable of on-wafer recording the 2D EUV flux distribution without any external power. The compact 2T EUV detector pixels arranged in a test array are capable of on-wafer recording the 2D EUV flux distribution without any external power. Through proper initialization process, EUV induced discharging mechanism is fully investigated and an EUV induced electron emission efficiency model is established. Finally, a 2D array for in-situ EUV detection is demonstrated to precisely reflect the pattern projected on the chip/wafer surface.

A Wireless, Mechanically Flexible, 25μm-Thick, 65,536-Channel Subdural Surface Recording and Stimulating Microelectrode Array with Integrated Antennas

This paper presents a fully wireless microelectrode array (MEA) system-on-chip (SoC) with 65,536 electrodes for non-penetrative cortical recording and stimulation, featuring a total sensing area of 6.8mm×7.4mm with a 26.5μm×29μm electrode pitch. Sensing, data telemetry, and powering are monolithically integrated on a single chip, which is made mechanically flexible to conform to the surface of the brain by substrate removal to a total thickness of 25μm allowing it to be contained entirely in the subdural space under the skull.

Monolithic Three-Dimensional Integration of Carbon Nanotube Circuits and Sensors for Smart Sensing Chips

Semiconducting carbon nanotube (CNT) film is a promising material for constructing high-performance complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) and highly sensitive field-effect transistor (FET) bio/chemical sensors. Moreover, CNT logic transistors and sensors can be integrated through a compatible low-temperature fabrication process, providing enough thermal budget to construct monolithic three-dimensional (M3D) systems for smart sensors. However, an M3D sensing chip based on CNT film has not yet been demonstrated. In this work, we develop M3D technology to fabricate CNT CMOS ICs and CNT sensor arrays in two different layers; then, we demonstrate a preliminary M3D sensing system comprising CNT CMOS interfacing ICs in the bottom layer and CNT sensors in the upper layer through interlayer vias as links. As a typical example, a highly sensitive hydrogen sensing IC has been demonstrated to perform in situ sensing and processing functions through upper-layer FET-based hydrogen sensors exposed to the environment and bottom-layer CNT CMOS voltage-controlled oscillator (VCO) interfacing circuits. The M3D CNT sensing ICs convert hydrogen concentration information (8-128 ppm) to digital frequency information (0.78-1.11 GHz) with a sensitivity of 2.75 MHz/ppm. M3D sensing technology is expected to provide a universal sensing system for future smart sensing chips, including multitarget detection and ultralow power sensors.

Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET

FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe channels. In this work, we develop an optimizing strategy of the Ge fraction in SiGe Channels of SGOI FinFET devices. The simulation results of ring oscillator (RO) circuits and SRAM cells reveal that altering the Ge fraction can improve the performance and power of different circuits for different applications.

Design and Measurement of Microelectromechanical Three-Axis Magnetic Field Sensors Based on the CMOS Technique

The design, fabrication, and measurement of a microelectromechanical system (MEMS) three-axis magnetic field sensor (MFS) based on the commercial complementary metal oxide semiconductor (CMOS) process are investigated. The MFS is a magnetic transistor type. The performance of the MFS was analyzed employing the semiconductor simulation software, Sentaurus TCAD. In order to decrease the cross-sensitivity of the three-axis MFS, the structure of the MFS is planed to accommodate two independent sensing components, a z-MFS utilized to sense magnetic field (M-F) in the z-direction and a y/x-MFS composed of a y-MFS and a x-MFS to be utilized to sense M-F in the y- and x-directions. The z-MFS incorporates four additional collectors to increase its sensitivity. The commercial 1P6M 0.18 μm CMOS process of the Taiwan Semiconductor Manufacturing Company (TSMC) is utilized to manufacture the MFS. Experiments depict that the MFS has a low cross-sensitivity of less than 3%. The sensitivities of z-, y-, and x-MFS are 237 mV/T, 485 mV/T, and 484 mV/T, respectively.

Measuring and modeling macrophage proliferation in a lab-on-CMOS capacitance sensing microsystem

We report on the use of a lab-on-CMOS biosensor platform for quantitatively tracking the proliferation of RAW 264.7 murine Balb/c macrophages. We show that macrophage proliferation correlates linearly with an average capacitance growth factor resulting from capacitance measurements at a plurality of electrodes dispersed in a sensing area of interest. We further show a temporal model that captures the cell number evolution in the area over long periods (e.g., 30 h). The model links the cell numbers and the average capacitance growth factor to describe the observed cell proliferation.

Classification of nucleic acid amplification on ISFET arrays using spectrogram-based neural networks

The COVID-19 pandemic has highlighted a significant research gap in the field of molecular diagnostics. This has brought forth the need for AI-based edge solutions that can provide quick diagnostic results whilst maintaining data privacy, security and high standards of sensitivity and specificity. This paper presents a novel proof-of-concept method to detect nucleic acid amplification using ISFET sensors and deep learning. This enables the detection of DNA and RNA on a low-cost and portable lab-on-chip platform for identifying infectious diseases and cancer biomarkers. We show that by using spectrograms to transform the signal to the time-frequency domain, image processing techniques can be applied to achieve the reliable classification of the detected chemical signals. Transformation to spectrograms is beneficial as it makes the data compatible with 2D convolutional neural networks and helps gain significant performance improvement over neural networks trained on the time domain data. The trained network achieves an accuracy of 84% with a size of 30kB making it suitable for deployment on edge devices. This facilitates a new wave of intelligent lab-on-chip platforms that combine microfluidics, CMOS-based chemical sensing arrays and AI-based edge solutions for more intelligent and rapid molecular diagnostics.

Automatic Piecewise Extreme Learning Machine-Based Model for S-Parameters of RF Power Amplifier

This paper presents an automatic piecewise (Auto-PW) extreme learning machine (ELM) method for S-parameters modeling radio-frequency (RF) power amplifiers (PAs). A strategy based on splitting regions at the changing points of concave-convex characteristics is proposed, where each region adopts a piecewise ELM model. The verification is carried out with S-parameters measured on a 2.2-6.5 GHz complementary metal oxide semiconductor (CMOS) PA. Compared to the long-short term memory (LSTM), support vector regression (SVR), and conventional ELM modeling methods, the proposed method performs excellently. For example, the modeling speed is two orders of magnitude faster than SVR and LSTM, and the modeling accuracy is more than one order of magnitude higher than ELM.

Room-Temperature CMOS Monolithic Resonant Triple-Band Terahertz Thermal Detector

Multiband terahertz (THz) detectors show great application potential in imaging, spectroscopy, and sensing fields. Thermal detectors have become a promising choice because they could sense THz radiations on the whole spectrum. This paper demonstrates the operation principle, module designs with in-depth theoretical analysis, and experimental validation of a room-temperature CMOS monolithic resonant triple-band THz thermal detector. The detector, which consists of a compact triple-band octagonal ring antenna and a sensitive proportional to absolute temperature (PTAT) sensor, has virtues of room-temperature operation, low cost, easy integration, and mass production. Good experimental results are obtained at 0.91 THz, 2.58 THz, and 4.2 THz with maximum responsivities of 32.6 V/W, 43.2 V/W, and 40 V/W, respectively, as well as NEPs of 1.28 μW/Hz^0.5, 2.19 μW/Hz^0.5, and 2.37 μW/Hz^0.5, respectively, providing great potential for multiband THz sensing and imaging systems.

A Wide-Bandwidth PVT-Reconfigurable CMOS Power Amplifier with an Integrated Tunable-Output Impedance Matching Network

This paper proposes a wideband CMOS power amplifier (PA) with integrated digitally assisted wideband pre-distorter (DAWPD) and a transformer-integrated tunable-output impedance matching network. As a continuation of our previous research, which focused only on linearization tuning for wideband and PVT, this work emphasized improving the maximum output power, gain and PAE across the PVT variations while maintaining the linearity for a wide frequency bandwidth of 1 GHz. The DAWPD is employed at the driver stage to realize a pre-distorting characteristic for wideband linearization. The addition of the tunable-output impedance matching technique in this work provides stable output power, PAE and gain across the PVT variations, through which it improves the design's robustness, reliability and production yield. Fabricated in CMOS 130 nm with an 8-metal-layer process, the DAWPD-PA with tunable-output impedance matching can achieve an operating frequency bandwidth of 1 GHz from 1.7 to 2.7 GHz. The DAWPD-PA attained a maximum output power of 27 to 28 dBm with a peak PAE of 38.8 to 41.3%. The power gain achieved was 26.9 to 29.7 dB across the targeted frequencies. In addition, when measured with a 20 MHz LTE modulated signal, the DAWPD-PA achieved a linear output power and PAE of 24.0 to 25.1 dBm and 34.5 to 38.8% across the frequency, respectively. On top of that, in this study, the DAWPD-PA is proven to be resilient to process-voltage-temperature (PVT) variations, where it achieves stable performances via the utilization of the proposed tuning mechanisms, mainly contributed by the proposed transformer-integrated tunable-output impedance matching network.

High-Sensitivity CMOS-Integrated Floating Gate-Based UVC Sensors

We report on novel UVC sensors based on the floating gate (FG) discharge principle. The device operation is similar to that of EPROM non-volatile memories UV erasure, but the sensitivity to ultraviolet light is strongly increased by using single polysilicon devices of special design with low FG capacitance and long gate periphery (grilled cells). The devices were integrated without additional masks into a standard CMOS process flow featuring a UV-transparent back end. Low-cost integrated UVC solar blind sensors were optimized for implementation in UVC sterilization systems, where they provided feedback on the radiation dose sufficient for disinfection. Doses of ~10 µJ/cm² at 220 nm could be measured in less than a second. The device can be reprogrammed up to 10,000 times and used to control ~10-50 mJ/cm² UVC radiation doses typically employed for surface or air disinfection. Demonstrators of integrated solutions comprising UV sources, sensors, logics, and communication means were fabricated. Compared with the existing silicon-based UVC sensing devices, no degradation effects that limit the targeted applications were observed. Other applications of the developed sensors, such as UVC imaging, are also discussed.

Combining n-MOS Charge Sensing with p-MOS Silicon Hole Double Quantum Dots in a CMOS platform

Holes in silicon quantum dots are receiving attention due to their potential as fast, tunable, and scalable qubits in semiconductor quantum circuits. Despite this, challenges remain in this material system including difficulties using charge sensing to determine the number of holes in a quantum dot, and in controlling the coupling between adjacent quantum dots. We address these problems by fabricating an ambipolar complementary metal-oxide-semiconductor (CMOS) device using multilayer palladium gates. The device consists of an electron charge sensor adjacent to a hole double quantum dot. We demonstrate control of the spin state via electric dipole spin resonance. We achieve smooth control of the interdot coupling rate over 1 order of magnitude and use the charge sensor to perform spin-to-charge conversion to measure the hole singlet-triplet relaxation time of 11 μs for a known hole occupation. These results provide a path toward improving the quality and controllability of hole spin-qubits.

CMOS Radio Frequency Energy Harvester (RFEH) with Fully On-Chip Tunable Voltage-Booster for Wideband Sensitivity Enhancement

Radio frequency energy harvesting (RFEH) is one form of renewable energy harvesting currently seeing widespread popularity because many wireless electronic devices can coordinate their communications via RFEH, especially in CMOS technology. For RFEH, the sensitivity of detecting low-power ambient RF signals is the utmost priority. The voltage boosting mechanisms at the input of the RFEH are typically applied to enhance its sensitivity. However, the bandwidth in which its sensitivity is maintained is very poor. This work implements a tunable voltage boosting (TVB) mechanism fully on-chip in a 3-stage cross-coupled differential drive rectifier (CCDD). The TVB is designed with an interleaved transformer architecture where the primary winding is implemented to the rectifier, while the secondary winding is connected to a MOSFET switch that tunes the inductance of the network. The TVB enables the sensitivity of the rectifier to be maintained at 1V DC output voltage with a minimum deviation of -2 dBm across a wide bandwidth of 3 to 6 GHz of 5G New Radio frequency (5GNR) bands. A DC output voltage of 1 V and a peak PCE of 83% at 3 GHz for -23 dBm input power are achieved. A PCE of more than 50% can be maintained at the sensitivity point of 1 V with the aid of TVB. The proposed CCDD-TVB mechanism enables the CMOS RFEH to be operated for wideband applications with optimum sensitivity, DC output voltage, and efficiency.

Analysis and Design of a Non-Magnetic Bulk CMOS Passive Circulator Using 25% Duty-Cycle Clock

A circulator, which is a non-reciprocal device, is widely used in full-duplex systems, future communication and sensing networks, and quantum computing, and it is difficult to implement a passive topology on a chip. Based on switch-based spatio-temporal conductivity modulation, in this study, we design and implement a non-magnetic on-chip passive circulator operating at the Ku band in a 90-nm bulk CMOS technology using a 25% duty-cycle I/Q clock signal. With the virtue of the four-phase non-overlapping clock signal, the proposed circulator achieves a 3.9 dB transmitter (TX)-to-antenna (ANT) and a 4.0 dB ANT-to-receiver (RX) insertion loss with a 1-dB bandwidth of 2.7 GHz (21.4%). The TX-to-RX isolation is better than 17.2 dB, and the TX-to-ANT IIP3 and ANT-to-RX IIP3 are 19.7 dBm and 20.0 dBm, respectively, while occupying a die area of 1.55 mm × 1.15 mm. Although low-cost bulk CMOS technology is used, competitive isolation, linearity performance, and isolation bandwidth are achieved in the proposed design.

Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks-an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm². The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.

Uniformity Correction of CMOS Image Sensor Modules for Machine Vision Cameras

Flat-field correction (FFC) is commonly used in image signal processing (ISP) to improve the uniformity of image sensor pixels. Image sensor nonuniformity and lens system characteristics have been known to be temperature-dependent. Some machine vision applications, such as visual odometry and single-pixel airborne object tracking, are extremely sensitive to pixel-to-pixel sensitivity variations. Numerous cameras, especially in the fields of infrared imaging and staring cameras, use multiple calibration images to correct for nonuniformities. This paper characterizes the temperature and analog gain dependence of the dark signal nonuniformity (DSNU) and photoresponse nonuniformity (PRNU) of two contemporary global shutter CMOS image sensors for machine vision applications. An optimized hardware architecture is proposed to compensate for nonuniformities, with optional parametric lens shading correction (LSC). Three different performance configurations are outlined for different application areas, costs, and power requirements. For most commercial applications, the correction of LSC suffices. For both DSNU and PRNU, compensation with one or multiple calibration images, captured at different gain and temperature settings are considered. For more demanding applications, the effectiveness, external memory bandwidth, power consumption, implementation, and calibration complexity, as well as the camera manufacturability of different nonuniformity correction approaches were compared.

A Direct Feedback FVF LDO for High Precision FMCW Radar Sensors in 65-nm CMOS Technology

A direct feedback flipped voltage follower (FVF) LDO for a high-precision frequency-modulated continuous-wave (FMCW) radar is presented. To minimize the effect of the power supply ripple on the FMCW radar sensor's resolution, a folded cascode error amplifier (EA) was connected to the outer loop of the FVF to increase the open-loop gain. The direct feedback structure enhances the PSRR while minimizing the power supply ripple path and not compromising a transient response. The flipped voltage follower with a super source follower forms a fast feedback loop. The stability and parameter variation sensitivity of the multi-loop FVF LDO were analyzed through the state matrix decomposition. We implemented the FVF LDO in TSMC 65 nm CMOS technology. The fabricated FVF LDO supplied a maximum load current of 20 mA with a 1.2 V power supply. The proposed FVF LDO achieved a full-spectrum PSR with a low-frequency PSRR of 66 dB, unity-gain bandwidth of 469 MHz, and 20 ns transient settling time with a load current step from 1 mA to 20 mA.

A Wideband and Low-Power Distributed Cascode Mixer Using Inductive Feedback

A wideband and low-power distributed cascode mixer is implemented for future mobile communications. The distributed design inspired by the distributed amplifier (DA) enables a mixer to operate in a wide band. In addition, the cascode structure and inductive positive feedback design allow high conversion gain with low-power consumption. The proposed mixer is fabricated using a 130 nm commercial complementary metal-oxide-semiconductor (CMOS) process. It consists of three cascode gain cells and operates with a drain voltage of 1.5 V and a gate voltage of 0.5 to 0.7 V. The fabricated mixer exhibits conversion gain of -2.9 to 3.1 dB at the radio frequencies (RFs) of 4 to 30 GHz and -1.9 to 0.4 dB at RFs of 54 to 66 GHz under the conditions of 8 to 10 dBm of local oscillator (LO) power and 650 MHz of intermediate frequency (IF). The LO-RF isolation is more than 15 dB over the entire measurement band (0.2 to 67 GHz) as the RF and LO signals are applied to different transistors owing to the cascode structure. The total power consumption is only within 12 mW, and the chip size is 0.056 mm², making it possible to implement a compact mixer. The proposed mixer shows broadband characteristics covering from ultra-wideband (UWB) and the 28 GHz fifth-generation (5G) communication band to the 60 GHz wireless gigabit alliance (WiGig) band.

Integrating Microfluidics and Electronics in Point-of-Care Diagnostics: Current and Future Challenges

Point-of-Care (POC) diagnostics have gained increasing attention in recent years due to its numerous advantages over conventional diagnostic approaches. As proven during the recent COVID-19 pandemic, the rapidity and portability of POC testing improves the efficiency of healthcare services and reduces the burden on healthcare providers. There are hundreds of thousands of different applications for POC diagnostics, however, the ultimate requirement for the test is the same: sample-in and result-out. Many technologies have been implemented, such as microfluidics, semiconductors, and nanostructure, to achieve this end. The development of even more powerful POC systems was also enabled by merging multiple technologies into the same system. One successful example is the integration of microfluidics and electronics in POC diagnostics, which has simplified the sample handling process, reduced sample usage, and reduced the cost of the test. This review will analyze the current development of the POC diagnostic systems with the integration of microfluidics and electronics and discuss the future challenges and perspectives that researchers might have.

A 24 GHz CMOS Direct-Conversion RF Receiver with I/Q Mismatch Calibration for Radar Sensor Applications

A 24 GHz millimeter-wave direct-conversion radio-frequency (RF) receiver with wide-range and precise I/Q mismatch calibration is designed in 65 nm CMOS technology for radar sensor applications. The CMOS RF receiver is based on a quadrature direct-conversion architecture. Analytic relations are derived to clearly exhibit the individual contributions of the I/Q amplitude and phase mismatches to the image-rejection ratio (IRR) degradation, which provides a useful design guide for determining the range and resolution of the I/Q mismatch calibration circuit. The designed CMOS RF receiver comprises a low-noise amplifier, quadrature down-conversion mixer, baseband amplifier, and quadrature LO generator. Controlling the individual gate bias voltages of the switching FETs in the down-conversion mixer having a resistive load is found to induce significant changes at the amplitude and phase of the output signal. In the calibration process, the mixer gate bias tuning is first performed for the amplitude mismatch calibration, and the remaining phase mismatch is then calibrated out by the varactor capacitance tuning at the LO buffer's LC load. Implemented in 65 nm CMOS process, the RF receiver achieves 31.5 dB power gain, -35.2 dBm input-referred 1 dB compression power, and 4.8-7.1 dB noise figure across 22.5-26.1 GHz band, while dissipating 106.2 mA from a 1.2 V supply. The effectiveness of the proposed I/Q mismatch calibration is successfully verified by observing that the amplitude and phase mismatches are improved from 1.0-1.5 dB to 0.02-0.19 dB, and from 10.8-23.8 to 1.1-3.2 degrees, respectively.

An Indoor-Monitoring LiDAR Sensor for Patients with Alzheimer Disease Residing in Long-Term Care Facilities

This paper introduces an indoor-monitoring LiDAR sensor for patients with Alzheimer disease residing in long-term care facilities (LTCFs), and this sensor exploits an optoelectronic analog front-end (AFE) to detect light signals from targets by utilizing on-chip avalanche photodiodes (APDs) realized in a 180 nm CMOS process and a neural processing unit (NPU) used for motion detection and decisions, especially for incidents of falls occurring in LTCFs. The AFE consists of an on-chip CMOS P⁺/N-well APD, a linear-mode transimpedance amplifier, a post-amplifier, and a time-to-digital converter, whereas the NPU exploits network sparsity and approximate processing elements for low-power operation. This work provides a potential solution of low-cost, low-power, indoor-monitoring LiDAR sensors for patients with Alzheimer disease in LTCFs.

A CMOS compatible thermoelectric device made of crystalline silicon membranes with nanopores

Herein, we report the use of nanostructured crystalline silicon as a thermoelectric material and its integration into thermoelectric devices. The proof-of-concept relies on the partial suppression of lattice thermal conduction by introducing pores with dimensions scaling between the electron mean free path and the phonon mean free path. In other words, we artificially aimed at the well-known 'electron crystal and phonon glass' trade-off targeted in thermoelectricity. The devices were fabricated using CMOS-compatible processes and exhibited power generation up to 5.5 mW cm^-2under a temperature difference of 280 K. These numbers demonstrate the capability to power autonomous devices with environmental heat sources using silicon chips of centimeter square dimensions. We also report the possibility of using the developed devices for integrated thermoelectric cooling.

A Novel Terahertz Detector Based on Asymmetrical FET Array in 55-nm Standard CMOS Process

This paper reports a novel, one-dimensional dense array of asymmetrical metal-oxide-semiconductor field-effect-transistor (MOSFET) THz detector, which has been fabricated in GlobalFoundries 55-nm CMOS technology. Compared with other technologies, the Si-based complementary metal-oxide-semiconductor (CMOS) dominates in industrial applications, owing to its easier integration and lower cost. However, as the frequency increases, the return loss between the antenna and detector will increase. The proposed THz detector has a short-period grating structure formed by MOSFET fingers in the array, which can serve as an effective antenna to couple incident THz radiation into the FET channels. It not only solved the problem of return loss effectively, but also greatly reduced the detector area. Meanwhile, since the THz signal is rectified at both the source and drain electrodes to generate two current signals with equal amplitude but opposite directions, the source drain voltage is not provided to reduce the power consumption. This leads to a poor performance of the THz detector. Therefore, by using an asymmetric structure for the gate fingers position to replace the source drain voltage, the performance of the detector in the case of zero power consumption can be effectively improved. Compared with the symmetrical MOSFET THz detector, R_v is increased by 183.3% and NEP is decreased by 67.7%.

DECAL: A Reconfigurable Monolithic Active Pixel Sensor for Tracking and Calorimetry in a 180 nm Image Sensor Process

In this paper, we describe DECAL, a prototype Monolithic Active Pixel Sensor (MAPS) device designed to demonstrate the feasibility of both digital calorimetry and reconfigurability in ASICs for particle physics. The goal of this architecture is to help reduce the development and manufacturing costs of detectors for future colliders by developing a chip that can operate both as a digital silicon calorimeter and a tracking chip. The prototype sensor consists of a matrix of 64 × 64 55 μm pixels, and provides a readout at 40 MHz of the number of particles which have struck the matrix in the preceding 25 ns. It can be configured to report this as a total sum across the sensor (equivalent to the pad of an analogue calorimeter) or the sum per column (equivalent to a traditional strip detector). The design and operation of the sensor are described, and the results of chip characterisation are reported and compared to simulations.