Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications

A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including nine SPADs using 0.18 µm high-voltage CMOS technology. The gating circuit achieves rise and fall times of 480 ps and 280 ps, respectively, and a minimum full-width-at-half-maximum pulse width of 1.26 ns. Thanks to a fast and sensitive comparator, a detection threshold for avalanche events of less than 100 mV is possible. The power consumption of all nine channels is about 250 mW in total. This gating chip is used to characterize the integrated SPADs. A photon detection probability of around 50% at 9.9 V excess bias and for a wavelength of 635 nm is found.

Area and Bandwidth Enhancement of an n+/p-Well Dot Avalanche Photodiode in 0.35 μm CMOS Technology

This paper presents a CMOS-integrated dot avalanche photodiode (dot-APD) that features a small central n⁺/p-well hemispherical cathode/p-well structure circularly surrounded by an anode ring. The dot-APD enables wide hemispherical depletion, charge collection from a large volume, and a small multiplication region. These features result in a large light-sensitive area, high responsivity and bandwidth, and exceptionally low junction capacitance. The active area can be further expanded using a multi-dot structure, which is an array of several cathode/p-well dots with a shared anode. Experimental results show that a 5 × 5 multi-dot APD with an active area of 70 μm × 70 μm achieves a bandwidth of 1.8 GHz, a responsivity of 9.7 A/W, and a capacitance of 27 fF. The structure of the multi-dot APD allows for the design of APDs in various sizes that offer high bandwidth and responsivity as an optical detector for various applications while still maintaining a small capacitance.

Detecting WDM visible light signals by a single multi-color photodiode with MIMO processing

For the first time, to the best of our knowledge, we experimentally demonstrate that multiple-input-multiple-output (MIMO) processing allows using a single photodiode to detect simultaneously a wavelength-division multiplexing (WDM) visible light communications (VLC) signal. The photodiode has a triple junction, and when it is illuminated by a WDM signal, the junctions produce inherently three photocurrents that are unusable for detecting any of the WDM signals. However, by means of linear MIMO processing, we are able to recover the transmitted signals exactly. Bit error rate measurements confirm the effectiveness of the proposed solution. This opens a new scenario for practical WDM-VLC systems.

0.35 μm CMOS avalanche photodiode with high responsivity and responsivity-bandwidth product

A highly sensitive avalanche photodiode (APD) in 0.35 μm CMOS technology is presented. Due to a thick intrinsic absorption layer, a high responsivity at a low bias voltage, where the avalanche gain is 1, is combined with an excellent avalanche gain at high voltages to achieve a maximum overall responsivity of the APD of more than 10 kA/W. This responsivity exceeds that of other submicrometer CMOS APDs by a factor of more than 700. As a figure of merit the responsivity-bandwidth product is defined, and the achieved value of 23.46 A/W·GHz is 2.4 times higher than the values found in the literature.

An infrastructure for accurate characterization of single-event transients in digital circuits

We present the architecture and a detailed pre-fabrication analysis of a digital measurement ASIC facilitating long-term irradiation experiments of basic asynchronous circuits, which also demonstrates the suitability of the general approach for obtaining accurate radiation failure models developed in our FATAL project. Our ASIC design combines radiation targets like Muller C-elements and elastic pipelines as well as standard combinational gates and flip-flops with an elaborate on-chip measurement infrastructure. Major architectural challenges result from the fact that the latter must operate reliably under the same radiation conditions the target circuits are exposed to, without wasting precious die area for a rad-hard design. A measurement architecture based on multiple non-rad-hard counters is used, which we show to be resilient against double faults, as well as many triple and even higher-multiplicity faults. The design evaluation is done by means of comprehensive fault injection experiments, which are based on detailed Spice models of the target circuits in conjunction with a standard double-exponential current injection model for single-event transients (SET). To be as accurate as possible, the parameters of this current model have been aligned with results obtained from 3D device simulation models, which have in turn been validated and calibrated using micro-beam radiation experiments at the GSI in Darmstadt, Germany. For the latter, target circuits instrumented with high-speed sense amplifiers have been used for analog SET recording. Together with a probabilistic analysis of the sustainable particle flow rates, based on a detailed area analysis and experimental cross-section data, we can conclude that the proposed architecture will indeed sustain significant target hit rates, without exceeding the resilience bound of the measurement infrastructure.