A 2D Heterostructure-Based Multifunctional Floating Gate Memory Device for Multimodal Reservoir Computing

The demand for economical and efficient data processing has led to a surge of interest in neuromorphic computing based on emerging two-dimensional (2D) materials in recent years. As a rising van der Waals (vdW) p-type Weyl semiconductor with many intriguing properties, tellurium (Te) has been widely used in advanced electronics/optoelectronics. However, its application in floating gate (FG) memory devices for information processing has never been explored. Herein, an electronic/optoelectronic FG memory device enabled by Te-based 2D vdW heterostructure for multimodal reservoir computing (RC) is reported. When subjected to intense electrical/optical stimuli, the device exhibits impressive nonvolatile electronic memory behaviors including ≈108 extinction ratio, ≈100 ns switching speed, >4000 cycles, >4000-s retention stability, and nonvolatile multibit optoelectronic programmable characteristics. When the input stimuli weaken, the nonvolatile memory degrades into volatile memory. Leveraging these rich nonlinear dynamics, a multimodal RC system with high recognition accuracy of 90.77% for event-type multimodal handwritten digit-recognition is demonstrated.

2D Dual Gate Field-Effect Transistor Enabled Versatile Functions

Advanced computing technologies such as distributed computing and the Internet of Things require highly integrated and multifunctional electronic devices. Beyond the Si technology, 2D-materials-based dual-gate transistors are expected to meet these demands due to the ultra-thin body and the dangling-bond-free surface. In this work, a molybdenum disulfide (MoS2 ) asymmetric-dual-gate field-effect transistor (ADGFET) with an In2 Se3 top gate and a global bottom gate is designed. The independently controlled double gates enable the device to achieve an on/off ratio of 106 with a low subthreshold swing of 94.3 mV dec-1 while presenting a logic function. The coupling effect between the double gates allows the top gate to work as a charge-trapping layer, realizing nonvolatile memory (105 on/off ratio with retention time over 104 s) and six-level memory states. Additionally, ADGFET displays a tunable photodetection with the responsivity reaching the highest value of 857 A W-1 , benefiting from the interface coupling between the double gates. Meanwhile, the photo-memory property of ADGFET is also verified by using the varying exposure dosages-dependent illumination. The multifunctional applications demonstrate that the ADGFET provides an alternative way to integrate logic, memory, and sensing into one device architecture.

Uncovering the Role of Crystal Phase in Determining Nonvolatile Flash Memory Device Performance Fabricated from MoTe2-Based 2D van der Waals Heterostructures

Although the crystal phase of two-dimensional (2D) transition metal dichalcogenides (TMDs) has been proven to play an essential role in fabricating high-performance electronic devices in the past decade, its effect on the performance of 2D material-based flash memory devices still remains unclear. Here, we report the exploration of the effect of MoTe₂ in different phases as the charge-trapping layer on the performance of 2D van der Waals (vdW) heterostructure-based flash memory devices, where a metallic 1T'-MoTe₂ or semiconducting 2H-MoTe₂ nanoflake is used as the floating gate. By conducting comprehensive measurements on the two kinds of vdW heterostructure-based devices, the memory device based on MoS₂/h-BN/1T'-MoTe₂ presents much better performance, including a larger memory window, faster switching speed (100 ns), and higher extinction ratio (10⁷), than that of the device based on the MoS₂/h-BN/2H-MoTe₂ heterostructure. Moreover, the device based on the MoS₂/h-BN/1T'-MoTe₂ heterostructure also shows a long cycle (>1200 cycles) and retention (>3000 s) stability. Our study clearly demonstrates that the crystal phase of 2D TMDs has a significant impact on the performance of nonvolatile flash memory devices based on 2D vdW heterostructures, which paves the way for the fabrication of future high-performance memory devices based on 2D materials.

High-Sensitivity CMOS-Integrated Floating Gate-Based UVC Sensors

We report on novel UVC sensors based on the floating gate (FG) discharge principle. The device operation is similar to that of EPROM non-volatile memories UV erasure, but the sensitivity to ultraviolet light is strongly increased by using single polysilicon devices of special design with low FG capacitance and long gate periphery (grilled cells). The devices were integrated without additional masks into a standard CMOS process flow featuring a UV-transparent back end. Low-cost integrated UVC solar blind sensors were optimized for implementation in UVC sterilization systems, where they provided feedback on the radiation dose sufficient for disinfection. Doses of ~10 µJ/cm² at 220 nm could be measured in less than a second. The device can be reprogrammed up to 10,000 times and used to control ~10-50 mJ/cm² UVC radiation doses typically employed for surface or air disinfection. Demonstrators of integrated solutions comprising UV sources, sensors, logics, and communication means were fabricated. Compared with the existing silicon-based UVC sensing devices, no degradation effects that limit the targeted applications were observed. Other applications of the developed sensors, such as UVC imaging, are also discussed.

Fully Photoswitchable Phototransistor Memory Comprising Perovskite Quantum Dot-Based Hybrid Nanocomposites as a Photoresponsive Floating Gate

Tremendous research efforts have been dedicated into the field of photoresponsive nonvolatile memory devices owing to their advantages of fast transmitting speed, low latency, and power-saving property that are suitable for replacing current electrical-driven electronics. However, the reported memory devices still rely on the assistance of gate bias to program them, and a real fully photoswitchable transistor memory is still rare. Herein, we report a phototransistor memory device comprising polymer/perovskite quantum dot (QD) hybrid nanocomposites as a photoresponsive floating gate. The perovskite QDs offer an effective discreteness with an excellent photoresponse that are suitable for photogate application. In addition, a series of ultraviolet (UV)-sensitive insulating polymer hosts were designed to investigate the effect of UV light on the memory behavior. We found that a fully photoswitchable memory device was fulfilled by using the independent and sequential photoexcitation between a UV-sensitive polymer host and a visible light-sensitive QD photogates, which produced decent photoresponse, memory switchability, and highly stable memory retention with a memory ratio of 10⁴ over 10⁴ s. This study not only unraveled the mystery in the fully photoswitchable functionality of nonvolatile memory but also enlightened their potential in the next-generation electronics for light-fidelity application.

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the charge leakage was reduced because of the formation of a carrier depletion zone at the junction interface serving as an intrinsic potential barrier. Additionally, the threshold voltage and erasing voltage of the np-type floating gate were elevated, suggesting that the performance of the floating gate in the operation of memory devices can be effectively improved without the application of new materials or changes to the physical structure.

A Machine Learning Attack Resilient True Random Number Generator Based on Stochastic Programming of Atomically Thin Transistors

A true random number generator (TRNG) is a critical hardware component that has become increasingly important in the era of Internet of Things (IoT) and mobile computing for ensuring secure communication and authentication schemes. While recent years have seen an upsurge in TRNGs based on nanoscale materials and devices, their resilience against machine learning (ML) attacks remains unexamined. In this article, we demonstrate a ML attack resilient, low-power, and low-cost TRNG by exploiting stochastic programmability of floating gate (FG) field effect transistors (FETs) with atomically thin channel materials. The origin of stochasticity is attributed to the probabilistic nature of charge trapping and detrapping phenomena in the FG. Our TRNG also satisfies other requirements, which include high entropy, uniformity, uniqueness, and unclonability. Furthermore, the generated bit-streams pass NIST randomness tests without any postprocessing. Our findings are important in the context of hardware security for resource constrained IoT edge devices, which are becoming increasingly vulnerable to ML attacks.

Low Optical Writing Energy Multibit Optoelectronic Memory Based on SnS2 /h-BN/Graphene Heterostructure

With the rapid development of artificial intelligence and neural network computing, the requirement for information storage in computing is gradually increasing. Floating gate memories based on 2D materials has outstanding characteristics such as non-volatility, optical writing, and optical storage, suitable for application in photonic in-memory computing chips. Notably, the optoelectronic memory requires less optical writing energy, which means lower power consumption and greater storage levels. Here, the authors report an optoelectronic memory based on SnS₂ /h-BN/graphene heterostructure with an extremely low photo-generated hole tunneling barrier of 0.23 eV. This non-volatile multibit floating gate memory shows a high switching ratio of 10⁶ and a large memory window range of 64.8 V in the gate range ±40 V. And the memory device can achieve multilevel storage states of 50 under a low power light pulses of 0.32 nW and small light pulse width of 50 ms. Thanks to the Fowler-Nordheim tunneling of the photo-generated holes, the optical writing energy of the optoelectronic memory has been successfully reduced by one to three orders of magnitude compared to existing 2D materials-based systems.

Contribution of Polymers to Electronic Memory Devices and Applications

Electronic memory devices, such as memristors, charge trap memory, and floating-gate memory, have been developed over the last decade. The use of polymers in electronic memory devices enables new opportunities, including easy-to-fabricate processes, mechanical flexibility, and neuromorphic applications. This review revisits recent efforts on polymer-based electronic memory developments. The versatile contributions of polymers for emerging memory devices are classified, providing a timely overview of such unconventional functionalities with a strong emphasis on the merits of polymer utilization. Furthermore, this review discusses the opportunities and challenges of polymer-based memory devices with respect to their device performance and stability for practical applications.

Photoinduced-reset and multilevel storage transistor memories based on antimony-doped tin oxide nanoparticles floating gate

Recently, antimony-doped tin oxide nanoparticles (ATO NPs) have been widely used in the fields of electronics, photonics, photovoltaics, sensing, and other fields because of their good conductivity, easy synthesis, excellent chemical stability, high mechanical strength, good dispersion and low cost. Herein, for the first time, a novel nonvolatile transistor memory device is fabricated using ATO NPs as charge trapping sites to enhance the memory performance. The resulting organic nano-floating gate memory (NFGM) device exhibits outstanding memory properties, including tremendous memory window (∼85 V), superhigh memory on/off ratio (∼10⁹), long data retention (over 10 years) and eminent multilevel storage behavior, which are among the optimal performances in NFGM devices based on organic field effect transistors. Additionally, the device displays photoinduced-reset characteristic with low energy consumption erasing operation. This study provides novel avenues for the manufacture of simple and low-cost data storage devices with outstanding memory performance, multilevel storage behavior and suitability as platforms for integrated circuits.

Artificial Synapses Based on Lead-Free Perovskite Floating-Gate Organic Field-Effect Transistors for Supervised and Unsupervised Learning

Synaptic devices are expected to overcome von Neumann's bottleneck and served as one of the foundations for future neuromorphic computing. Lead halide perovskites are considered as promising photoactive materials but limited by the toxicity of lead. Herein, lead-free perovskite CsBi₃I₁₀ is utilized as a photoactive material to fabricate organic synaptic transistors with a floating-gate structure for the first time. The devices can maintain the I_light/I_dark ratio of 10³ for 4 h and have excellent stability within the 30 days test even without encapsulation. Synaptic functions are successfully simulated. Notably, by combining the decent charge transport property of the organic semiconductor and the excellent photoelectronic property of CsBi₃I₁₀, synaptic performance can be realized even with an operating voltage as low as -0.01 V, which is rare among floating-gate synaptic transistors. Furthermore, artificial neural networks are constructed. We propose a new method that can simulate the synaptic weight value in multiple digit form to achieve complete gradient descent. The image recognition test exhibits thrilling recognition accuracy for both supervised (91%) and unsupervised (81%) classifications. These results demonstrate the great potential of floating-gate organic synaptic transistors in neuromorphic computing.

Modeling of Quasi-Static Floating-Gate Transistor Biosensors

Floating-gate transistors (FGTs) are a promising class of electronic sensing architectures that separate the transduction elements from molecular sensing components, but the factors leading to optimum device design are unknown. We developed a model, generalizable to many different semiconductor/dielectric materials and channel dimensions, to predict the sensor response to changes in capacitance and/or charge at the sensing surface upon target binding or other changes in surface chemistry. The model predictions were compared to experimental data obtained using a floating-gate (extended gate) electrochemical transistor, a variant of the generic FGT architecture that facilitates low-voltage operation and rapid, simple fabrication using printing. Self-assembled monolayer (SAM) chemistry and quasi-statically measured resistor-loaded inverters were utilized to obtain experimentally either the capacitance signals (with alkylthiol SAMs) or charge signals (with acid-terminated SAMs) of the FGT. Experiments reveal that the model captures the inverter gain and charge signals over 3 orders of magnitude variation in the size of the sensing area and the capacitance signals over 2 orders of magnitude but deviates from experiments at lower capacitances of the sensing surface (<1 nF). To guide future device design, model predictions for a large range of sensing area capacitances and characteristic voltages are provided, enabling the calculation of the optimum sensing area size for maximum charge and capacitance sensitivity.

Comprehensive Non-volatile Photo-programming Transistor Memory via a Dual-Functional Perovskite-Based Floating Gate

Photonic transistor memory has received increasing attention as next-generation optoelectronic devices for light fidelity (Li-Fi) application due to the attractive advantages of ultra-speed, high security, and low power consumption. However, most transistor-type photonic memories developed to date still rely on electrical bias for operation, imposing certain limits on data transmission efficiency and energy consumption. In this study, the dual manipulation of "photo-writing" and "photo-erasing" of a novel photonic transistor memory is successfully realized by cleverly utilizing the complementary light absorption between the photoactive material, n-type BPE-PTCDI, in the active channel and the hybrid floating gate, CH₃NH₃PbBr₃/poly(2-vinylpyridine). The fabricated device not only can be operated under the full spectrum but also shows stable switching cycles of photo-writing (PW)-reading (R)-photo-erasing (PE)-reading (R) (PW-R-PE-R) with a high memory ratio of ∼10⁴, and the memory characteristics possess a stable long-term retention of >10⁴ s. Notably, photo-erasing only requires 1 s light illumination. Due to the fully optical functionality, the rigid gate electrode is removed and a novel two-terminal flexible photonic memory is fabricated. The device not only exhibits stable electrical performance after 1000 bending cycles but also manifests a multilevel functional behavior, demonstrating a promising potential for the future development of photoactive electronic devices.

A Non-Volatile Tunable Terahertz Metamaterial Absorber Using Graphene Floating Gate

Based on the graphene floating gate, a tunable terahertz metamaterial absorber is proposed. Compared with the traditional graphene–dielectric–metal absorber, our absorber has the property of being non-volatile and capacity for anti-interference. Using the finite element method, the paper investigates the absorption spectra, the electric field energy distribution, the tunability and the physical mechanism. In addition, we also analyse the influence of geometry, polarization and incident angles on the absorption. Simulation results show that the bandwidth of the absorption above 90% can reach up to 2.597 THz at the center frequency of 3.970 THz, and the maximum absorption can be tuned continuously from 14.405% to 99.864% by controlling the Fermi level from 0 eV to 0.8 eV. Meanwhile, the proposed absorber has the advantages of polarization insensitivity and a wide angle, and has potential applications in imaging, sensing and photoelectric detection.

Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage

The memory window of floating gate (FG) type non-volatile memory (NVM) devices is a fundamental figure of merit used not only to evaluate the performance, such as retention and endurance, but also to discuss the feasibility of advanced functional memory devices. However, the memory window of 2D materials based NVM devices is historically determined from round sweep transfer curves, while that of conventional Si NVM devices is determined from high and low threshold voltages (V_th s), which are measured by single sweep transfer curves. Here, it is elucidated that the memory window of 2D NVM devices determined from round sweep transfer curves is overestimated compared with that determined from single sweep transfer curves. The floating gate voltage measurement proposed in this study clarifies that the V_th s in round sweep are controlled not only by the number of charges stored in floating gate but also by capacitive coupling between floating gate and back gate. The present finding on the overestimation of memory window enables to appropriately evaluate the potential of 2D NVM devices.

Two-Dimensional Cs2Pb(SCN)2Br2-Based Photomemory Devices Showing a Photoinduced Recovery Behavior and an Unusual Fully Optically Driven Memory Behavior

The rapid development of Internet of Things and big data has made the conventional storage devices face the need of reforming. Rather than using electrical pulses to store data in one of two states, photomemory exploiting optical stimulation to store light information emerges as a revolutionary candidate for the optoelectronic community. However, fully optically driven photomemory with fast data transmission speed and outstanding energy saving capability suffers from less exploration. Herein, a transistor-type photomemory using a 2D Cs₂Pb(SCN)₂Br₂/polymer hybrid floating gate is explored and three host polymers, polystyrene, poly(4-vinylphenol), and poly(vinylpyrrolidone) (PVP), are investigated to understand the relationship between polymer matrix selection and memory performance. All devices show a photoinduced recovery memory behavior but with two distinctly different photomemory behaviors. In addition to the demonstration of a regular nonvolatile photomemory showing a high on/off ratio of >10⁶ over 10⁴ s, an unusual fully optically driven memory behavior is intriguingly accomplished in the Cs₂Pb(SCN)₂Br₂/PVP photomemory. Using white light as the driver of programming and a blue laser as the main performer of erasing, this device can be switched between two distinguishable states and possesses acceptable data discriminability, as evidenced by its fully optically driven writing (programing)-reading-erasing-reading switching function that shows an on/off current ratio of 10³. This study not only presents the first 2D perovskite-based photomemory but also shows a novel fully optically driven memory that has been rarely reported in the literature.

Double-Gate MoS2 Field-Effect Transistor with a Multilayer Graphene Floating Gate: A Versatile Device for Logic, Memory, and Synaptic Applications

2D materials with low-temperature processing hold promise for electronic devices that augment conventional silicon technology. To meet this promise, devices should have capabilities not easily achieved with silicon technology, including planar fully-depleted silicon-on-insulator with substrate body-bias, or vertical finFETs with no body-bias capability. In this work, we fabricate and characterize a device [a double-gate MoS₂ field-effect transistor (FET) with hexagonal boron nitride (h-BN) gate dielectrics and a multi-layer graphene floating gate (FG)] in multiple operating conditions to demonstrate logic, memory, and synaptic applications; a range of h-BN thicknesses is investigated for charge retention in the FG. In particular, we demonstrate this device as a (i) logic FET with adjustable V_T by charges stored in the FG, (ii) digital flash memory with lower pass-through voltage to enable improved reliability, and (iii) synaptic device with decoupling of tunneling and gate dielectrics to achieve a symmetric program/erase conductance change. Overall, this versatile device, compatible to back-end-of-line integration, could readily augment silicon technology.

A Floating Gate Memory with U-Shape Recessed Channel for Neuromorphic Computing and MCU Applications

We have simulated a U-shape recessed channel floating gate memory by Sentaurus TCAD tools. Since the floating gate (FG) is vertically placed between source (S) and drain (D), and control gate (CG) and HfO₂ high-k dielectric extend above source and drain, the integrated density can be well improved, while the erasing and programming speed of the device are respectively decreased to 75 ns and 50 ns. In addition, comprehensive synaptic abilities including long-term potentiation (LTP) and long-term depression (LTD) are demonstrated in our U-shape recessed channel FG memory, highly resembling the biological synapses. These simulation results show that our device has the potential to be well used as embedded memory in neuromorphic computing and MCU (Micro Controller Unit) applications.

Negative Photoconductance in van der Waals Heterostructure-Based Floating Gate Phototransistor

van der Waals (vdW) heterostructures made of two-dimensional materials have been demonstrated to be versatile architectures for optoelectronic applications due to strong light--matter interactions. However, most light-controlled phenomena and applications in the vdW heterostructures rely on positive photoconductance (PPC). Negative photoconductance (NPC) has not yet been reported in vdW heterostructures. Here we report the observation of the NPC in the ReS₂/h-BN/MoS₂ vdW heterostructure-based floating gate phototransistor. The fabricated devices exhibit excellent performance of nonvolatile memory without light illumination. More interestingly, we observe a gate-tunable transition between the PPC and the NPC under the light illumination. The observed NPC phenomenon can be attributed to charge transfer between the floating gate and the conduction channel. Furthermore, we show that control of NPC through light intensity is promising in realization of light-tunable multibit memory devices. Our results may enable potential applications in multifunctional memories and optoelectronic devices.

Nanoscale Tipping Bucket Effect in a Quantum Dot Transistor-Based Counter

Electronic circuits composed of one or more elements with inherent memory, that is, memristors, memcapacitors, and meminductors, offer lower circuit complexity and enhanced functionality for certain computational tasks. Networks of these elements are proposed for novel computational paradigms that rely on information processing and storage on the same physical platform. We show a nanoscaled memdevice able to act as an electronic analogue of tipping buckets that allows reducing the dimensionality and complexity of a sensing problem by transforming it into a counting problem. The device offers a well adjustable, tunable, and reliable periodic reset that is controlled by the amounts of transferred quantum dot charges per gate voltage sweep. When subjected to periodic voltage sweeps, the quantum dot (bucket) may require up to several sweeps before a rapid full discharge occurs thus displaying period doubling, period tripling, and so on between self-governing reset operations.

Detecting 100 fW cm-2 Light with Trapped Electron Gated Organic Phototransistors

Ultraweak light detection with solid-state and cooling-free photodetectors is important for both fundamental research and practical applications. A general phototransistor architecture for detecting ultraviolet-visible light down to 100 fW cm^-2 at room temperature is demonstrated. The exceptional sensitivity stems from an amplification process triggered by incident light. A responsivity of ≈10⁷ A W^-1 is achieved.

Effects of Ambient Air and Temperature on Ionic Gel Gated Single-Walled Carbon Nanotube Thin-Film Transistor and Circuits

Single-walled carbon nanotube thin-film transistor (SWCNT TFT) and circuits were fabricated by fully inkjet printing gold nanoparticles as source/drain electrodes, semiconducting SWCNT thin films as channel materials, PS-PMMA-PS/EMIM TFSI composite gel as gate dielectrics, and PEDOT/PSS as gate electrodes. The ionic gel gated SWCNT TFT shows reversible conversion from p-type transistor behavior in air to ambipolar features under vacuum due to reversible oxygen doping in semiconducting SWCNT thin films. The threshold voltages of ionic gel gated SWCNT TFT and inverters are largely shifted to the low value (0.5 V for p-region and 1.0 V for n-region) by vacuum annealing at 140 °C to exhausively remove water that is incorporated in the ionic gel as floating gates. The vacuum annealed ionic gel gated SWCNT TFT shows linear temperature dependent transconductances and threshold voltages for both p- and n-regions. The strong temperature dependent transconductances (0.08 μS/K for p-region, 0.4 μS/K for n-region) indicate their potential application in thermal sensors. In the other hand, the weak temperature dependent threshold voltages (-1.5 mV/K for p-region, -1.1 mV/K for n-region) reflect their excellent thermal stability.