Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

Ultra high-throughput single molecule spectroscopy with a 1024 pixel SPAD

Single-molecule spectroscopy is a powerful approach to measuring molecular properties such as size, brightness, conformation, and binding constants. Due to the low concentrations in the single-molecule regime, measurements with good statistical accuracy require long acquisition times. Previously we showed a factor of 8 improvement in acquisition speed using a custom-CMOS 8x1 SPAD array. Here we present preliminary results with a 64X improvement in throughput obtained using a liquid crystal on silicon spatial light modulator (LCOS-SLM) and a novel standard CMOS 1024 pixel SPAD array, opening the way to truly high-throughput single-molecule spectroscopy.

Ultra-miniature wireless temperature sensor for thermal medicine applications

This study presents a prototype design of an ultra-miniature, wireless, battery-less, and implantable temperature-sensor, with applications to thermal medicine such as cryosurgery, hyperthermia, and thermal ablation. The design aims at a sensory device smaller than 1.5 mm in diameter and 3 mm in length, to enable minimally invasive deployment through a hypodermic needle. While the new device may be used for local temperature monitoring, simultaneous data collection from an array of such sensors can be used to reconstruct the 3D temperature field in the treated area, offering a unique capability in thermal medicine. The new sensory device consists of three major subsystems: a temperature-sensing core, a wireless data-communication unit, and a wireless power reception and management unit. Power is delivered wirelessly to the implant from an external source using an inductive link. To meet size requirements while enhancing reliability and minimizing cost, the implant is fully integrated in a regular foundry CMOS technology (0.15 μm in the current study), including the implant-side inductor of the power link. A temperature-sensing core that consists of a proportional-to-absolute-temperature (PTAT) circuit has been designed and characterized. It employs a microwatt chopper stabilized op-amp and dynamic element-matched current sources to achieve high absolute accuracy. A second order sigma-delta (Σ-Δ) analog-to-digital converter (ADC) is designed to convert the temperature reading to a digital code, which is transmitted by backscatter through the same antenna used for receiving power. A high-efficiency multi-stage differential CMOS rectifier has been designed to provide a DC supply to the sensing and communication subsystems. This paper focuses on the development of the all-CMOS temperature sensing core circuitry part of the device, and briefly reviews the wireless power delivery and communication subsystems.

Advances in CMOS Solid-state Photomultipliers for Scintillation Detector Applications

Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes the characterization and performance of these devices for scintillation detector applications. This work also describes the terms contributing to device noise in terms of the excess noise of the SSPM, the binomial statistics governing the number of pixels triggered by a scintillation event, and the background, or thermal, count rate. The fluctuations associated with these terms limit the resolution of the signal pulse amplitude. We explore the use of pixel-level signal conditioning, and characterize the performance of a prototype SSPM device that preserves the digital nature of the signal. In addition, we explore designs of position-sensitive SSPM detectors for medical imaging applications, and characterize their performance.

CMOS-integrated film bulk acoustic resonators for label-free biosensing

The throughput is an important parameter for label-free biosensors. Acoustic resonators like the quartz crystal microbalance have a low throughput because the number of sensors which can be used at the same time is limited. Here we present an array of 64 CMOS-integrated film bulk acoustic resonators. We compare the performance with surface plasmon resonance and the quartz crystal microbalance and demonstrate the performance of the sensor for multiplexed detection of DNA.

Ultra-high-speed image signal accumulation sensor

Averaging of accumulated data is a standard technique applied to processing data with low signal-to-noise ratios (SNR), such as image signals captured in ultra-high-speed imaging. The authors propose an architecture layout of an ultra-high-speed image sensor capable of on-chip signal accumulation. The very high frame rate is enabled by employing an image sensor structure with a multi-folded CCD in each pixel, which serves as an in situ image signal storage. The signal accumulation function is achieved by direct connection of the first and the last storage elements of the in situ storage CCD. It has been thought that the multi-folding is achievable only by driving electrodes with complicated and impractical layouts. Simple configurations of the driving electrodes to overcome the difficulty are presented for two-phase and four-phase transfer CCD systems. The in situ storage image sensor with the signal accumulation function is named Image Signal Accumulation Sensor (ISAS).

A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System

We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented.

Implantable CMOS Biomedical Devices

The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented.

CMOS Image Sensor with a Built-in Lane Detector

This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature.

CMOS Image Sensors for High Speed Applications

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

Standard CMOS Fabrication of a Sensitive Fully Depleted Electrolyte-Insulator-Semiconductor Field Effect Transistor for Biosensor Applications

Microfabricated semiconductor devices are becoming increasingly relevant for detection of biological and chemical components. The integration of active biological materials together with sensitive transducers offers the possibility of generating highly sensitive, specific, selective and reliable biosensors. This paper presents the fabrication of a sensitive, fully depleted (FD), electrolyte-insulator-semiconductor field-effect transistor (EISFET) made with a silicon-on-insulator (SOI) wafer of a thin 10-30 nm active SOI layer. Initial results are presented for device operation in solutions and for bio-sensing. Here we report the first step towards a high volume manufacturing of a CMOS-based biosensor that will enable various types of applications including medical and environmental sensing.

Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels

In this paper we present a novel, quadruple well process developed in a modern 0.18 μm CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 μm pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency.

CMOS Humidity Sensor System Using Carbon Nitride Film as Sensing Materials

An integrated humidity sensor system with nano-structured carbon nitride film as humidity sensing material is fabricated by a 0.8 μm analog mixed CMOS process. The integrated sensor system consists of differential humidity sensitive field effect transistors (HUSFET), temperature sensor, and operational amplifier. The process contains two poly, two metal and twin well technology. To form CN_x film on Si₃N₄/Si substrate, plasma etching is performed to the gate area as well as trenches. CN_x film is deposited by reactive RF magnetron sputtering method and patterned by the lift-off technique. The drain current is proportional to the dielectric constant, and the sensitivity is 2.8 μA/%RH.

Electro-Physical Technique for Post-Fabrication Measurements of CMOS Process Layer Thicknesses

This paper presents a combined physical and electrical post-fabrication method for determining the thicknesses of the various layers in a commercial 1.5 μm complementary-metal-oxide-semiconductor (CMOS) foundry process available through MOSIS. Forty-two thickness values are obtained from physical step-height measurements performed on thickness test structures and from electrical measurements of capacitances, sheet resistances, and resistivities. Appropriate expressions, numeric values, and uncertainties for each layer of thickness are presented, along with a systematic nomenclature for interconnect and dielectric thicknesses. However, apparent inconsistencies between several of the physical and electrical results for film thickness suggest that further uncertainty analysis is required and the effects of several assumptions need to be quantified.

Simple Thermal-Efficiency Model for CMOS-Microhotplate Design

Simple, semi-empirical, first-order, analytic approximations to the current, voltage, and power as a function of microhotplate temperature are derived. To lowest order, the voltage is independent of, and the power and current are inversely proportional to, the length of the microhotplate heater legs. A first-order design strategy based on this result is described.