Memristor-Based Analog Computation and Neural Network Classification with a Dot Product Engine

Multimodal Artificial Synapses for Neuromorphic Application

The rapid development of neuromorphic computing has led to widespread investigation of artificial synapses. These synapses can perform parallel in-memory computing functions while transmitting signals, enabling low-energy and fast artificial intelligence. Robots are the most ideal endpoint for the application of artificial intelligence. In the human nervous system, there are different types of synapses for sensory input, allowing for signal preprocessing at the receiving end. Therefore, the development of anthropomorphic intelligent robots requires not only an artificial intelligence system as the brain but also the combination of multimodal artificial synapses for multisensory sensing, including visual, tactile, olfactory, auditory, and taste. This article reviews the working mechanisms of artificial synapses with different stimulation and response modalities, and presents their use in various neuromorphic tasks. We aim to provide researchers in this frontier field with a comprehensive understanding of multimodal artificial synapses.

Biomimetic Neuromorphic Sensory System via Electrolyte Gated Transistors

Biomimetic neuromorphic sensing systems, inspired by the structure and function of biological neural networks, represent a major advancement in the field of sensing technology and artificial intelligence. This review paper focuses on the development and application of electrolyte gated transistors (EGTs) as the core components (synapses and neuros) of these neuromorphic systems. EGTs offer unique advantages, including low operating voltage, high transconductance, and biocompatibility, making them ideal for integrating with sensors, interfacing with biological tissues, and mimicking neural processes. Major advances in the use of EGTs for neuromorphic sensory applications such as tactile sensors, visual neuromorphic systems, chemical neuromorphic systems, and multimode neuromorphic systems are carefully discussed. Furthermore, the challenges and future directions of the field are explored, highlighting the potential of EGT-based biomimetic systems to revolutionize neuromorphic prosthetics, robotics, and human-machine interfaces. Through a comprehensive analysis of the latest research, this review is intended to provide a detailed understanding of the current status and future prospects of biomimetic neuromorphic sensory systems via EGT sensing and integrated technologies.

Stochastic switching and analog-state programmable memristor and its utilization for homomorphic encryption hardware

Homomorphic encryption performs computations on encrypted data without decrypting, thereby eliminating security issues during the data communication between clouds and edges. As a result, there is a growing need for homomorphic encryption hardware (HE-HW) for the edges, where low power consumption and a compact form factor are desired. Here, a Pt/Ta2O5/Mo metallic cluster-type memristors (Mo-MCM) characterized by the Mo as a mobile species, and its utilization for the HE-HW via a 1-trasistor-1-memristor (1T1M) array as a prototype HE-HW is proposed. The Mo-MCM exhibits inherent stochastic set-switching behavior, which can be utilized for generating the random numbers required for encryption key generation. Furthermore, the device can accurately store analog conductance states after set-switching, which can be used as an analog non-volatile memristor. By simultaneously leveraging these two characteristics, encryption key generation, data encryption, and decryption are possible within a single device through an in-memory computing manner.

Reservoir computing with a random memristor crossbar array

Physical implementations of reservoir computing (RC) based on the emerging memristors have become promising candidates of unconventional computing paradigms. Traditionally, sequential approaches by time-multiplexing volatile memristors have been prevalent because of their low hardware overhead. However, they suffer from the problem of speed degradation and fall short of capturing the spatial relationship between the time-domain inputs. Here, we explore a new avenue for RC using memristor crossbar arrays with device-to-device variations, which serve as physical random weight matrices of the reservoir layers, enabling faster computation thanks to the parallelism of matrix-vector multiplication as an intensive operation in RC. To achieve this new RC architecture, ultralow-current, self-selective memristors are fabricated and integrated without the need of transistors, showing greater potential of high scalability and three-dimensional integrability compared to the previous realizations. The information processing ability of our RC system is demonstrated in asks of recognizing digit images and waveforms. This work indicates that the 'nonidealities' of the emerging memristor devices and circuits are a useful source of inspiration for new computing paradigms.

Hardware implementation of backpropagation using progressive gradient descent for in situ training of multilayer neural networks

Neural network training can be slow and energy-expensive due to the frequent transfer of weight data between digital memory and processing units. Neuromorphic systems can accelerate neural networks by performing multiply-accumulate operations in parallel using nonvolatile analog memory. However, executing the widely used backpropagation training algorithm in multilayer neural networks requires information-and therefore storage-of the partial derivatives of the weight values preventing suitable and scalable implementation in hardware. Here, we propose a hardware implementation of the backpropagation algorithm that progressively updates each layer using in situ stochastic gradient descent, avoiding this storage requirement. We experimentally demonstrate the in situ error calculation and the proposed progressive backpropagation method in a multilayer hardware-implemented neural network. We confirm identical learning characteristics and classification performance compared to conventional backpropagation in software. We show that our approach can be scaled to large and deep neural networks, enabling highly efficient training of advanced artificial intelligence computing systems.

Heterogeneous density-based clustering with a dual-functional memristive array

In the big data era, the requirement for data clustering methods that can handle massive and heterogeneous datasets with varying distributions increases. This study proposes a clustering algorithm for data sets with heterogeneous density using a dual-mode memristor crossbar array for data clustering. The array consists of a Ta/HfO2/RuO2 memristor operating in analog or digital modes, controlled by the reset voltage. The digital mode shows low dispersion and a high resistance ratio, and the analog mode enables precise conductance tuning. The local outlier factor is introduced to handle a heterogeneous density, and the required Euclidean and K-distances within the given dataset are calculated in the analog mode in parallel. In the digital mode, clustering is performed based on the connectivity among data points after excluding the detected outliers. The proposed algorithm boasts linear time complexity for the entire process. Extensive evaluations of synthetic datasets demonstrate significant improvement over representative density-based algorithms, and the datasets with heterogeneous density are clustered feasibly. Finally, the proposed algorithm is used to cluster the single-molecule localization microscopy data, demonstrating the feasibility of the suggested method for real-world problems.

Memristive Monte Carlo DropConnect crossbar array enabled by device and algorithm co-design

Device and algorithm co-design aims to develop energy-efficient hardware that directly implements complex algorithms and optimizes algorithms to match the hardware's characteristics. Specifically, neuromorphic computing algorithms are constantly growing in complexity, necessitating an ongoing search for hardware implementations capable of handling these intricate algorithms. Here, we present a memristive Monte Carlo DropConnect (MC-DC) crossbar array developed through a hardware algorithm co-design approach. To implement the MC-DC neural network, stochastic switching and analog memory characteristics are required, and we achieved them using Ag-based diffusive selectors and Ru-based electrochemical metalization (ECM) memristors, respectively. The devices were integrated with a one-selector one-memristor (1S1M) structure, and their well-matched operating voltages and currents enabled stochastic readout and deterministic analog programming. With the integrated hardware, we successfully demonstrated the MC-DC operation. Additionally, the selector allowed for the control of switching polarity, and by understanding this hardware characteristic, we were able to modify the algorithm to fit it and further improve the network performance.

HDR vision sensor with neuro-memristive skin detection for edge computing

Human skin classification is an essential task for several machine vision applications such as human-machine interfaces, people/object tracking, and classification. In this paper, we describe a hybrid CMOS/memristor vision sensor architecture embedding skin detection over a wide dynamic range. In-sensor RGB to r g-chromaticity color-space conversion is executed on-the-fly through a pixel-level automatic exposure time control. Each pixel of the array delivers two pre-filtered analog signals, the r and g values, suitable for being efficiently classified as skin or non-skin through an analog memristive neural network (NN), without the need for any further signal processing. Moreover, we study the NN performance and theorize how it should be added in the hardware. The skin classifier is organized in an array of column-level memristor-based NN to exploit the nano-scale device characteristics and non-volatile analog memory capabilities, making the proposed sensor architecture highly flexible, customizable for various use-case scenarios, and low-power. The output is a skin bitmap that is robust against variations of the illuminant color and intensity.

A comprehensive review of advanced trends: from artificial synapses to neuromorphic systems with consideration of non-ideal effects

A neuromorphic system is composed of hardware-based artificial neurons and synaptic devices, designed to improve the efficiency of neural computations inspired by energy-efficient and parallel operations of the biological nervous system. A synaptic device-based array can compute vector-matrix multiplication (VMM) with given input voltage signals, as a non-volatile memory device stores the weight information of the neural network in the form of conductance or capacitance. However, unlike software-based neural networks, the neuromorphic system unavoidably exhibits non-ideal characteristics that can have an adverse impact on overall system performance. In this study, the characteristics required for synaptic devices and their importance are discussed, depending on the targeted application. We categorize synaptic devices into two types: conductance-based and capacitance-based, and thoroughly explore the operations and characteristics of each device. The array structure according to the device structure and the VMM operation mechanism of each structure are analyzed, including recent advances in array-level implementation of synaptic devices. Furthermore, we reviewed studies to minimize the effect of hardware non-idealities, which degrades the performance of hardware neural networks. These studies introduce techniques in hardware and signal engineering, as well as software-hardware co-optimization, to address these non-idealities through compensation approaches.

Memristor-Based Neuromorphic Chips

In the era of information, characterized by an exponential growth in data volume and an escalating level of data abstraction, there has been a substantial focus on brain-like chips, which are known for their robust processing power and energy-efficient operation. Memristors are widely acknowledged as the optimal electronic devices for the realization of neuromorphic computing, due to their innate ability to emulate the interconnection and information transfer processes witnessed among neurons. This review paper focuses on memristor-based neuromorphic chips, which provide an extensive description of the working principle and characteristic features of memristors, along with their applications in the realm of neuromorphic chips. Subsequently, a thorough discussion of the memristor array, which serves as the pivotal component of the neuromorphic chip, as well as an examination of the present mainstream neural networks, is delved. Furthermore, the design of the neuromorphic chip is categorized into three crucial sections, including synapse-neuron cores, networks on chip (NoC), and neural network design. Finally, the key performance metrics of the chip is highlighted, as well as the key metrics related to the memristor devices are employed to realize both the synaptic and neuronal components.

Hardware implementation of memristor-based artificial neural networks

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.

Recent Advances in In-Memory Computing: Exploring Memristor and Memtransistor Arrays with 2D Materials

The conventional computing architecture faces substantial challenges, including high latency and energy consumption between memory and processing units. In response, in-memory computing has emerged as a promising alternative architecture, enabling computing operations within memory arrays to overcome these limitations. Memristive devices have gained significant attention as key components for in-memory computing due to their high-density arrays, rapid response times, and ability to emulate biological synapses. Among these devices, two-dimensional (2D) material-based memristor and memtransistor arrays have emerged as particularly promising candidates for next-generation in-memory computing, thanks to their exceptional performance driven by the unique properties of 2D materials, such as layered structures, mechanical flexibility, and the capability to form heterojunctions. This review delves into the state-of-the-art research on 2D material-based memristive arrays, encompassing critical aspects such as material selection, device performance metrics, array structures, and potential applications. Furthermore, it provides a comprehensive overview of the current challenges and limitations associated with these arrays, along with potential solutions. The primary objective of this review is to serve as a significant milestone in realizing next-generation in-memory computing utilizing 2D materials and bridge the gap from single-device characterization to array-level and system-level implementations of neuromorphic computing, leveraging the potential of 2D material-based memristive devices.

Novel Three-Dimensional Artificial Neural Network Based on an Eight-Layer Vertical Memristor with an Ultrahigh Rectify Ratio (>107) and an Ultrahigh Nonlinearity (>105) for Neuromorphic Computing

In recent years, memristors have successfully demonstrated their significant potential in artificial neural networks (ANNs) and neuromorphic computing. Nonetheless, ANNs constructed by crossbar arrays suffer from cross-talk issues and low integration densities. Here, we propose an eight-layer three-dimensional (3D) vertical crossbar memristor with an ultrahigh rectify ratio (RR > 107) and an ultrahigh nonlinearity (>105) to overcome these limitations, which enables it to reach a >1 Tb array size without reading failure. Furthermore, the proposed 3D RRAM shows advanced endurance (>1010 cycles), retention (>104 s), and uniformity. In addition, several synaptic functions observed in the human brain were mimicked. On the basis of the advanced performance, we constructed a novel 3D ANN, whose learning efficiency and recognition accuracy were enhanced significantly compared with those of conventional single-layer ANNs. These findings hold promise for the development of highly efficient, precise, integrated, and stable VLSI neuromorphic computing systems.

Memristor-based storage system with convolutional autoencoder-based image compression network

The exponential growth of various complex images is putting tremendous pressure on storage systems. Here, we propose a memristor-based storage system with an integrated near-storage in-memory computing-based convolutional autoencoder compression network to boost the energy efficiency and speed of the image compression/retrieval and improve the storage density. We adopt the 4-bit memristor arrays to experimentally demonstrate the functions of the system. We propose a step-by-step quantization aware training scheme and an equivalent transformation for transpose convolution to improve the system performance. The system exhibits a high (>33 dB) peak signal-to-noise ratio in the compression and decompression of the ImageNet and Kodak24 datasets. Benchmark comparison results show that the 4-bit memristor-based storage system could reduce the latency and energy consumption by over 20×/5.6× and 180×/91×, respectively, compared with the server-grade central processing unit-based/the graphics processing unit-based processing system, and improve the storage density by more than 3 times.

Implementation of Convolutional Neural Networks in Memristor Crossbar Arrays with Binary Activation and Weight Quantization

We propose a hardware-friendly architecture of a convolutional neural network using a 32 × 32 memristor crossbar array having an overshoot suppression layer. The gradual switching characteristics in both set and reset operations enable the implementation of a 3-bit multilevel operation in a whole array that can be utilized as 16 kernels. Moreover, a binary activation function mapped to the read voltage and ground is introduced to evaluate the result of training with a boundary of 0.5 and its estimated gradient. Additionally, we adopt a fixed kernel method, where inputs are sequentially applied to a crossbar array with a differential memristor pair scheme, reducing unused cell waste. The binary activation has robust characteristics against device state variations, and a neuron circuit is experimentally demonstrated on a customized breadboard. Thanks to the analogue switching characteristics of the memristor device, the accurate vector-matrix multiplication (VMM) operations can be experimentally demonstrated by combining sequential inputs and the weights obtained through tuning operations in the crossbar array. In addition, the feature images extracted by VMM during the hardware inference operations on 100 test samples are classified, and the classification performance by off-chip training is compared with the software results. Finally, inference results depending on the tolerance are statistically verified through several tuning cycles.

Purely self-rectifying memristor-based passive crossbar array for artificial neural network accelerators

Memristor-integrated passive crossbar arrays (CAs) could potentially accelerate neural network (NN) computations, but studies on these devices are limited to software-based simulations owing to their poor reliability. Herein, we propose a self-rectifying memristor-based 1 kb CA as a hardware accelerator for NN computations. We conducted fully hardware-based single-layer NN classification tasks involving the Modified National Institute of Standards and Technology database using the developed passive CA, and achieved 100% classification accuracy for 1500 test sets. We also investigated the influences of the defect-tolerance capability of the CA, impact of the conductance range of the integrated memristors, and presence or absence of selection functionality in the integrated memristors on the image classification tasks. We offer valuable insights into the behavior and performance of CA devices under various conditions and provide evidence of the practicality of memristor-integrated passive CAs as hardware accelerators for NN applications.

Self-Rectifying Memristors for Three-Dimensional In-Memory Computing

Costly data movement in terms of time and energy in traditional von Neumann systems is exacerbated by emerging information technologies related to artificial intelligence. In-memory computing (IMC) architecture aims to address this problem. Although the IMC hardware prototype represented by a memristor is developed rapidly and performs well, the sneak path issue is a critical and unavoidable challenge prevalent in large-scale and high-density crossbar arrays, particularly in three-dimensional (3D) integration. As a perfect solution to the sneak-path issue, a self-rectifying memristor (SRM) is proposed for 3D integration because of its superior integration density. To date, SRMs have performed well in terms of power consumption (aJ level) and scalability (>102  Mbit). Moreover, SRM-configured 3D integration is considered an ideal hardware platform for 3D IMC. This review focuses on the progress in SRMs and their applications in 3D memory, IMC, neuromorphic computing, and hardware security. The advantages, disadvantages, and optimization strategies of SRMs in diverse application scenarios are illustrated. Challenges posed by physical mechanisms, fabrication processes, and peripheral circuits, as well as potential solutions at the device and system levels, are also discussed.

Filament-free memristors for computing

Memristors have attracted increasing attention due to their tremendous potential to accelerate data-centric computing systems. The dynamic reconfiguration of memristive devices in response to external electrical stimuli can provide highly desirable novel functionalities for computing applications when compared with conventional complementary-metal-oxide-semiconductor (CMOS)-based devices. Those most intensively studied and extensively reviewed memristors in the literature so far have been filamentary type memristors, which typically exhibit a relatively large variability from device to device and from switching cycle to cycle. On the other hand, filament-free switching memristors have shown a better uniformity and attractive dynamical properties, which can enable a variety of new computing paradigms but have rarely been reviewed. In this article, a wide range of filament-free switching memristors and their corresponding computing applications are reviewed. Various junction structures, switching properties, and switching principles of filament-free memristors are surveyed and discussed. Furthermore, we introduce recent advances in different computing schemes and their demonstrations based on non-filamentary memristors. This Review aims to present valuable insights and guidelines regarding the key computational primitives and implementations enabled by these filament-free switching memristors.

Reconfigurable Neuromorphic Computing: Materials, Devices, and Integration

Neuromorphic computing has been attracting ever-increasing attention due to superior energy efficiency, with great promise to promote the next wave of artificial general intelligence in the post-Moore era. Current approaches are, however, broadly designed for stationary and unitary assignments, thus encountering reluctant interconnections, power consumption, and data-intensive computing in that domain. Reconfigurable neuromorphic computing, an on-demand paradigm inspired by the inherent programmability of brain, can maximally reallocate finite resources to perform the proliferation of reproducibly brain-inspired functions, highlighting a disruptive framework for bridging the gap between different primitives. Although relevant research has flourished in diverse materials and devices with novel mechanisms and architectures, a precise overview remains blank and urgently desirable. Herein, the recent strides along this pursuit are systematically reviewed from material, device, and integration perspectives. At the material and device level, one comprehensively conclude the dominant mechanisms for reconfigurability, categorized into ion migration, carrier migration, phase transition, spintronics, and photonics. Integration-level developments for reconfigurable neuromorphic computing are also exhibited. Finally, a perspective on the future challenges for reconfigurable neuromorphic computing is discussed, definitely expanding its horizon for scientific communities.

Reliable Memristive Synapses Based on Parylene-MoOx Nanocomposites for Neuromorphic Applications

Memristive devices, known for their nonvolatile resistive switching, are promising components for next-generation neuromorphic computing systems, which mimic the brain's neural architecture. Specifically, these devices are well-suited for functioning as artificial synapses due to their analogue tunability and low energy consumption. However, the improvement of their performance and reliability remains a pressing challenge. In this study, we report the development and comprehensive characterization of memristive devices based on a parylene-MoOx (PPX-Mo) nanocomposite layer, which exhibit improved characteristics over their parylene-based counterparts: lower switching voltage and energy, smaller dispersion, and better resistive plasticity. A robust statistical analysis identified the optimal synthesis parameters for these devices, providing valuable insights for future device optimization. The most probable resistive switching mechanism of the devices is proposed. By successfully integrating these memristors into a neuromorphic computing model and showcasing their scalability in crossbar geometry, we demonstrate their potential as functional artificial synapses. The results obtained from this study can be useful for the development of hardware-brain-inspired computational systems.

Threshold plasticity of SOI-GST microring resonators

Spiking Neural Networks, also known as third generation Artificial Neural Networks, have widely attracted more attention because of their advantages of behaving more biologically interpretable and being more suitable for hardware implementation. Apart from using traditional synaptic plasticity, neural networks can also be based on threshold plasticity, achieving similar functionality. This can be implemented using e.g. the Bienenstock, Cooper and Munro rule. This is a classical unsupervised learning mechanism in which the threshold is closely related to the output of the post-synaptic neuron. We show in simulations that the threshold characteristics of the nonlinear effects of a microring resonator integrated with Ge2Sb2Te5 demonstrate some complex dependencies on the intracavity refractive index, attenuation, and wavelength detuning of the incident optical pulse, and exhibit class II excitability. We also show that we are able to modify the threshold power of the microring resonator by the changes of the refractive index and loss of Ge2Sb2Te5, due to transitions between the crystalline and amorphous states. Simulations show that the presented device exhibits both excitatory and inhibitory learning behavior, either lowering or raising the threshold.

Electro-Thermal Characterization of Dynamical VO2 Memristors via Local Activity Modeling

Translating the surging interest in neuromorphic electronic components, such as those based on nonlinearities near Mott transitions, into large-scale commercial deployment faces steep challenges in the current lack of means to identify and design key material parameters. These issues are exemplified by the difficulties in connecting measurable material properties to device behavior via circuit element models. Here, the principle of local activity is used to build a model of VO2 /SiN Mott threshold switches by sequentially accounting for constraints from a minimal set of quasistatic and dynamic electrical and high-spatial-resolution thermal data obtained via in situ thermoreflectance mapping. By combining independent data sets for devices with varying dimensions, the model is distilled to measurable material properties, and device scaling laws are established. The model can accurately predict electrical and thermal conductivities and capacitances and locally active dynamics (especially persistent spiking self-oscillations). The systematic procedure by which this model is developed has been a missing link in predictively connecting neuromorphic device behavior with their underlying material properties, and should enable rapid screening of material candidates before employing expensive manufacturing processes and testing procedures.

Memristor-based spiking neural network with online reinforcement learning

Neural networks implemented in memristor-based hardware can provide fast and efficient in-memory computation, but traditional learning methods such as error back-propagation are hardly feasible in it. Spiking neural networks (SNNs) are highly promising in this regard, as their weights can be changed locally in a self-organized manner without the demand for high-precision changes calculated with the use of information almost from the entire network. This problem is rather relevant for solving control tasks with neural-network reinforcement learning methods, as those are highly sensitive to any source of stochasticity in a model initialization, training, or decision-making procedure. This paper presents an online reinforcement learning algorithm in which the change of connection weights is carried out after processing each environment state during interaction-with-environment data generation. Another novel feature of the algorithm is that it is applied to SNNs with memristor-based STDP-like learning rules. The plasticity functions are obtained from real memristors based on poly-p-xylylene and CoFeB-LiNbO3 nanocomposite, which were experimentally assembled and analyzed. The SNN is comprised of leaky integrate-and-fire neurons. Environmental states are encoded by the timings of input spikes, and the control action is decoded by the first spike. The proposed learning algorithm solves the Cart-Pole benchmark task successfully. This result could be the first step towards implementing a real-time agent learning procedure in a continuous-time environment that can be run on neuromorphic systems with memristive synapses.

Electrochemical-Memristor-Based Artificial Neurons and Synapses-Fundamentals, Applications, and Challenges

Artificial neurons and synapses are considered essential for the progress of the future brain-inspired computing, based on beyond von Neumann architectures. Here, a discussion on the common electrochemical fundamentals of biological and artificial cells is provided, focusing on their similarities with the redox-based memristive devices. The driving forces behind the functionalities and the ways to control them by an electrochemical-materials approach are presented. Factors such as the chemical symmetry of the electrodes, doping of the solid electrolyte, concentration gradients, and excess surface energy are discussed as essential to understand, predict, and design artificial neurons and synapses. A variety of two- and three-terminal memristive devices and memristive architectures are presented and their application for solving various problems is shown. The work provides an overview of the current understandings on the complex processes of neural signal generation and transmission in both biological and artificial cells and presents the state-of-the-art applications, including signal transmission between biological and artificial cells. This example is showcasing the possibility for creating bioelectronic interfaces and integrating artificial circuits in biological systems. Prospectives and challenges of the modern technology toward low-power, high-information-density circuits are highlighted.

Compute in-Memory with Non-Volatile Elements for Neural Networks: A Review from a Co-Design Perspective

Deep learning has become ubiquitous, touching daily lives across the globe. Today, traditional computer architectures are stressed to their limits in efficiently executing the growing complexity of data and models. Compute-in-memory (CIM) can potentially play an important role in developing efficient hardware solutions that reduce data movement from compute-unit to memory, known as the von Neumann bottleneck. At its heart is a cross-bar architecture with nodal non-volatile-memory elements that performs an analog multiply-and-accumulate operation, enabling the matrix-vector-multiplications repeatedly used in all neural network workloads. The memory materials can significantly influence final system-level characteristics and chip performance, including speed, power, and classification accuracy. With an over-arching co-design viewpoint, this review assesses the use of cross-bar based CIM for neural networks, connecting the material properties and the associated design constraints and demands to application, architecture, and performance. Both digital and analog memory are considered, assessing the status for training and inference, and providing metrics for the collective set of properties non-volatile memory materials will need to demonstrate for a successful CIM technology.

Energy and Space Efficient Parallel Adder Using Molecular Memristors

A breakthrough in in-memory computing technologies hinges on the development of appropriate material platforms that can overcome their existing limitations, such as larger than optimal footprint and multiple serial computational steps, with potential accumulation of errors. Using a molecular switching element with multiple non-monotonic and deterministic transitions, the device count and the number of computational steps can be substantially reduced. With molecular materials, however, the realization of a reliable and robust platform is an unattained goal for decades. Here, crossbar arrays with up to 64 molecular memristors are fabricated to experimentally demonstrate 8-bit serial and 4-bit parallel adders that operate for thousands of measurement cycles with an estimated error probability of 10-16 . For performance benchmarking, a 32-bit parallel adder is designed and simulated with 268 million inputs including contributions from the peripheral circuitry showing a 47× higher energy efficiency, 93× faster operation, and 9% of the footprint, leading to 4390 times improved energy-delay product compared to a special purpose complementary metal-oxide-semiconductor (CMOS)-based multicore adder.

Star Memristive Neural Network: Dynamics Analysis, Circuit Implementation, and Application in a Color Cryptosystem

At present, memristive neural networks with various topological structures have been widely studied. However, the memristive neural network with a star structure has not been investigated yet. In order to investigate the dynamic characteristics of neural networks with a star structure, a star memristive neural network (SMNN) model is proposed in this paper. Firstly, an SMNN model is proposed based on a Hopfield neural network and a flux-controlled memristor. Then, its chaotic dynamics are analyzed by using numerical analysis methods including bifurcation diagrams, Lyapunov exponents, phase plots, Poincaré maps, and basins of attraction. The results show that the SMNN can generate complex dynamical behaviors such as chaos, multi-scroll attractors, and initial boosting behavior. The number of multi-scroll attractors can be changed by adjusting the memristor's control parameters. And the position of the coexisting chaotic attractors can be changed by switching the memristor's initial values. Meanwhile, the analog circuit of the SMNN is designed and implemented. The theoretical and numerical results are verified through MULTISIM simulation results. Finally, a color image encryption scheme is designed based on the SMNN. Security performance analysis shows that the designed cryptosystem has good security.

Interfacing Biology and Electronics with Memristive Materials

Memristive technologies promise to have a large impact on modern electronics, particularly in the areas of reconfigurable computing and artificial intelligence (AI) hardware. Meanwhile, the evolution of memristive materials alongside the technological progress is opening application perspectives also in the biomedical field, particularly for implantable and lab-on-a-chip devices where advanced sensing technologies generate a large amount of data. Memristive devices are emerging as bioelectronic links merging biosensing with computation, acting as physical processors of analog signals or in the framework of advanced digital computing architectures. Recent developments in the processing of electrical neural signals, as well as on transduction and processing of chemical biomarkers of neural and endocrine functions, are reviewed. It is concluded with a critical perspective on the future applicability of memristive devices as pivotal building blocks in bio-AI fusion concepts and bionic schemes.

Sparse matrix multiplication in a record-low power self-rectifying memristor array for scientific computing

Memristor-enabled in-memory computing provides an unconventional computing paradigm to surpass the energy efficiency of von Neumann computers. Owing to the limitation of the computing mechanism, while the crossbar structure is desirable for dense computation, the system's energy and area efficiency degrade substantially in performing sparse computation tasks, such as scientific computing. In this work, we report a high-efficiency in-memory sparse computing system based on a self-rectifying memristor array. This system originates from an analog computing mechanism that is motivated by the device's self-rectifying nature, which can achieve an overall performance of ~97 to ~11 TOPS/W for 2- to 8-bit sparse computation when processing practical scientific computing tasks. Compared to previous in-memory computing system, this work provides over 85 times improvement in energy efficiency with an approximately 340 times reduction in hardware overhead. This work can pave the road toward a highly efficient in-memory computing platform for high-performance computing.

Preventing Vanishing Gradient Problem of Hardware Neuromorphic System by Implementing Imidazole-Based Memristive ReLU Activation Neuron

With advances in artificial intelligent services, brain-inspired neuromorphic systems with synaptic devices are recently attracting significant interest to circumvent the von Neumann bottleneck. However, the increasing trend of deep neural network parameters causes huge power consumption and large area overhead of a nonlinear neuron electronic circuit, and it incurs a vanishing gradient problem. Here, a memristor-based compact and energy-efficient neuron device is presented to implement a rectifying linear unit (ReLU) activation function. To emulate the volatile and gradual switching of the ReLU function, a copolymer memristor with a hybrid structure is proposed using a copolymer/inorganic bilayer. The functional copolymer film developed by introducing imidazole functional groups enables the formation of nanocluster-type pseudo-conductive filaments by boosting the nucleation of Cu nanoclusters, causing gradual switching. The ReLU neuron device is successfully demonstrated by integrating the memristor with amorphous InGaZnO thin-film transistors, and achieves 0.5 pJ of energy consumption based on sub-10 µA operation current and high-speed switching of 650 ns. Furthermore, device-to-system-level simulation using neuron devices on the MNIST dataset demonstrates that the vanishing gradient problem is effectively resolved by five-layer deep neural networks. The proposed neuron device will enable the implementation of high-density and energy-efficient hardware neuromorphic systems.

Memristor-based neural networks: a bridge from device to artificial intelligence

Since the beginning of the 21st century, there is no doubt that the importance of artificial intelligence has been highlighted in many fields, among which the memristor-based artificial neural network technology is expected to break through the limitation of von Neumann so as to realize the replication of the human brain by enabling strong parallel computing ability and efficient data processing and become an important way towards the next generation of artificial intelligence. A new type of nanodevice, namely memristor, which is based on the variability of its resistance value, not only has very important applications in nonvolatile information storage, but also presents obsessive progressiveness in highly integrated circuits, making it one of the most promising circuit components in the post-Moore era. In particular, memristors can effectively simulate neural synapses and build neural networks; thus, they can be applied for the preparation of various artificial intelligence systems. This study reviews the research progress of memristors in artificial neural networks in detail and highlights the structural advantages and frontier applications of neural networks based on memristors. Finally, some urgent problems and challenges in current research are summarized and corresponding solutions and future development trends are put forward.

Stretchable Transistor-Structured Artificial Synapses for Neuromorphic Electronics

Stretchable synaptic transistors, a core technology in neuromorphic electronics, have functions and structures similar to biological synapses and can concurrently transmit signals and learn. Stretchable synaptic transistors are usually soft and stretchy and can accommodate various mechanical deformations, which presents significant prospects in soft machines, electronic skin, human-brain interfaces, and wearable electronics. Considerable efforts have been devoted to developing stretchable synaptic transistors to implement electronic device neuromorphic functions, and remarkable advances have been achieved. Here, this review introduces the basic concept of artificial synaptic transistors and summarizes the recent progress in device structures, functional-layer materials, and fabrication processes. Classical stretchable synaptic transistors, including electric double-layer synaptic transistors, electrochemical synaptic transistors, and optoelectronic synaptic transistors, as well as the applications of stretchable synaptic transistors in light-sensory systems, tactile-sensory systems, and multisensory artificial-nerves systems, are discussed. Finally, the current challenges and potential directions of stretchable synaptic transistors are analyzed. This review presents a detailed introduction to the recent progress in stretchable synaptic transistors from basic concept to applications, providing a reference for the development of stretchable synaptic transistors in the future.

Ultrathin Nitride Ferroic Memory with Large ON/OFF Ratios for Analog In-Memory Computing

Computing in the analog regime using nonlinear ferroelectric resistive memory arrays can potentially alleviate the energy constraints and complexity/footprint challenges imposed by digital von Neumann systems. Yet the current ferroelectric resistive memories suffer from either low ON/OFF ratios/imprint or limited compatibility with mainstream semiconductors. Here, for the first time, ferroelectric and analog resistive switching in an epitaxial nitride heterojunction comprising ultrathin (≈5 nm) nitride ferroelectrics, i.e., ScAlN, with potentiality to bridge the gap between performance and compatibility is demonstrated. High ON/OFF ratios (up to 10⁵ ), high uniformity, good retention, (<20% variation after > 10⁵  s) and cycling endurance (>10⁴ ) are simultaneously demonstrated in a metal/oxide/nitride ferroelectric junction. It is further demonstrated that the memristor can provide programmability to enable multistate operation and linear analogue computing as well as image processing with high accuracy. Neural network simulations based on the weight update characteristics of the nitride memory yielded an image recognition accuracy of 92.9% (baseline 96.2%) on the images from Modified National Institute of Standards and Technology. The non-volatile multi-level programmability and analog computing capability provide first-hand and landmark evidence for constructing advanced memory/computing architectures based on emerging nitride ferroelectrics, and promote homo and hybrid integrated functional edge devices beyond silicon.

Memristor-Based Signal Processing for Compressed Sensing

With the rapid progress of artificial intelligence, various perception networks were constructed to enable Internet of Things (IoT) applications, thereby imposing formidable challenges to communication bandwidth and information security. Memristors, which exhibit powerful analog computing capabilities, emerged as a promising solution expected to address these challenges by enabling the development of the next-generation high-speed digital compressed sensing (CS) technologies for edge computing. However, the mechanisms and fundamental properties of memristors for achieving CS remain unclear, and the underlying principles for selecting different implementation methods based on various application scenarios have yet to be elucidated. A comprehensive overview of memristor-based CS techniques is currently lacking. In this article, we systematically presented CS requirements on device performance and hardware implementation. The relevant models were analyzed and discussed from the mechanism level to elaborate the memristor CS system scientifically. In addition, the method of deploying CS hardware using the powerful signal processing capabilities and unique performance of memristors was further reviewed. Subsequently, the potential of memristors in all-in-one compression and encryption was anticipated. Finally, existing challenges and future outlooks for memristor-based CS systems were discussed.

Synaptic Resistor Circuits Based on Al Oxide and Ti Silicide for Concurrent Learning and Signal Processing in Artificial Intelligence Systems

Neurobiological circuits containing synapses can process signals while learning concurrently in real time. Before an artificial neural network (ANN) can execute a signal-processing program, it must first be programmed by humans or trained with respect to a large and defined data set during learning processes, resulting in significant latency, high power consumption, and poor adaptability to unpredictable changing environments. In this work, a crossbar circuit of synaptic resistors (synstors) is reported, each synstor integrating a Si channel with an Al oxide memory layer and Ti silicide Schottky contacts. Individual synstors are characterized and analyzed to understand their concurrent signal-processing and learning abilities. Without any prior training, synstor circuits concurrently execute signal processing and learning in real time to fly drones toward a target position in an aerodynamically changing environment faster than human controllers, and with learning speed, performance, power consumption, and adaptability to the environment significantly superior to an ANN running on computers. The synstor circuit provides a path to establish power-efficient intelligent systems with real-time learning and adaptability in the capriciously mutable real world.

A self-adaptive hardware with resistive switching synapses for experience-based neurocomputing

Neurobiological systems continually interact with the surrounding environment to refine their behaviour toward the best possible reward. Achieving such learning by experience is one of the main challenges of artificial intelligence, but currently it is hindered by the lack of hardware capable of plastic adaptation. Here, we propose a bio-inspired recurrent neural network, mastered by a digital system on chip with resistive-switching synaptic arrays of memory devices, which exploits homeostatic Hebbian learning for improved efficiency. All the results are discussed experimentally and theoretically, proposing a conceptual framework for benchmarking the main outcomes in terms of accuracy and resilience. To test the proposed architecture for reinforcement learning tasks, we study the autonomous exploration of continually evolving environments and verify the results for the Mars rover navigation. We also show that, compared to conventional deep learning techniques, our in-memory hardware has the potential to achieve a significant boost in speed and power-saving.

Highly Reliable Ovonic Threshold Switch with TiN/GeTe/TiN Structure

A new architecture has become necessary owing to the power consumption and latency problems of the von Neumann architecture. A neuromorphic memory system is a promising candidate for the new system as it has the potential to process large amounts of digital information. A crossbar array (CA), which consists of a selector and a resistor, is the basic building block for the new system. Despite the excellent prospects of crossbar arrays, the biggest obstacle for them is sneak current, which can cause a misreading between the adjacent memory cells, thus resulting in a misoperation in the arrays. The chalcogenide-based ovonic threshold switch (OTS) is a powerful selector with highly nonlinear I-V characteristics that can be used to address the sneak current problem. In this study, we evaluated the electrical characteristics of an OTS with a TiN/GeTe/TiN structure. This device shows nonlinear DC I-V characteristics, an excellent endurance of up to 10⁹ in the burst read measurement, and a stable threshold voltage below 15 mV/dec. In addition, at temperatures below 300 °C, the device exhibits good thermal stability and retains an amorphous structure, which is a strong indication of the aforementioned electrical characteristics.

Photonic online learning: a perspective

Emerging neuromorphic hardware promises to solve certain problems faster and with higher energy efficiency than traditional computing by using physical processes that take place at the device level as the computational primitives in neural networks. While initial results in photonic neuromorphic hardware are very promising, such hardware requires programming or "training" that is often power-hungry and time-consuming. In this article, we examine the online learning paradigm, where the machinery for training is built deeply into the hardware itself. We argue that some form of online learning will be necessary if photonic neuromorphic hardware is to achieve its true potential.

Transfer-free graphene passivation of sub 100 nm thin Pt and Pt–Cu electrodes for memristive devices

Memristive switches are among the most promising building blocks for future neuromorphic computing. These devices are based on a complex interplay of redox reactions on the nanoscale. Nanoionic phenomena enable non-linear and low-power resistance transition in ultra-short programming times. However, when not controlled, the same electrochemical reactions can result in device degradation and instability over time. Two-dimensional barriers have been suggested to precisely manipulate the nanoionic processes. But fabrication-friendly integration of these materials in memristive devices is challenging.Here we report on a novel process for graphene passivation of thin platinum and platinum/copper electrodes. We also studied the level of defects of graphene after deposition of selected oxides that are relevant for memristive switching.

Resistive Switching Crossbar Arrays Based on Layered Materials

Resistive switching (RS) devices are metal/insulator/metal cells that can change their electrical resistance when electrical stimuli are applied between the electrodes, and they can be used to store and compute data. Planar crossbar arrays of RS devices can offer a high integration density (>10⁸  devices mm^{- 2} ) and this can be further enhanced by stacking them three-dimensionally. The advantage of using layered materials (LMs) in RS devices compared to traditional phase-change materials and metal oxides is that their electrical properties can be adjusted with a higher precision. Here, the key figures-of-merit and procedures to implement LM-based RS devices are defined. LM-based RS devices fabricated using methods compatible with industry are identified and discussed. The focus is on small devices (size < 9 µm² ) arranged in crossbar structures, since larger devices may be affected by artifacts, such as grain boundaries and flake junctions. How to enhance device performance, so to accelerate the development of this technology, is also discussed.

Brain Organoid Computing for Artificial Intelligence

Brain-inspired hardware emulates the structure and working principles of a biological brain and may address the hardware bottleneck for fast-growing artificial intelligence (AI). Current brain-inspired silicon chips are promising but still limit their power to fully mimic brain function for AI computing. Here, we develop Brainoware , living AI hardware that harnesses the computation power of 3D biological neural networks in a brain organoid. Brain-like 3D in vitro cultures compute by receiving and sending information via a multielectrode array. Applying spatiotemporal electrical stimulation, this approach not only exhibits nonlinear dynamics and fading memory properties but also learns from training data. Further experiments demonstrate real-world applications in solving non-linear equations. This approach may provide new insights into AI hardware.

A review of memristor: material and structure design, device performance, applications and prospects

With the booming growth of artificial intelligence (AI), the traditional von Neumann computing architecture based on complementary metal oxide semiconductor devices are facing memory wall and power wall. Memristor based in-memory computing can potentially overcome the current bottleneck of computer and achieve hardware breakthrough. In this review, the recent progress of memory devices in material and structure design, device performance and applications are summarized. Various resistive switching materials, including electrodes, binary oxides, perovskites, organics, and two-dimensional materials, are presented and their role in the memristor are discussed. Subsequently, the construction of shaped electrodes, the design of functional layer and other factors influencing the device performance are analyzed. We focus on the modulation of the resistances and the effective methods to enhance the performance. Furthermore, synaptic plasticity, optical-electrical properties, the fashionable applications in logic operation and analog calculation are introduced. Finally, some critical issues such as the resistive switching mechanism, multi-sensory fusion, system-level optimization are discussed.

Organic Memristor with Synaptic Plasticity for Neuromorphic Computing Applications

Memristors have been considered to be more efficient than traditional Complementary Metal Oxide Semiconductor (CMOS) devices in implementing artificial synapses, which are fundamental yet very critical components of neurons as well as neural networks. Compared with inorganic counterparts, organic memristors have many advantages, including low-cost, easy manufacture, high mechanical flexibility, and biocompatibility, making them applicable in more scenarios. Here, we present an organic memristor based on an ethyl viologen diperchlorate [EV(ClO₄)]₂/triphenylamine-containing polymer (BTPA-F) redox system. The device with bilayer structure organic materials as the resistive switching layer (RSL) exhibits memristive behaviors and excellent long-term synaptic plasticity. Additionally, the device's conductance states can be precisely modulated by consecutively applying voltage pulses between the top and bottom electrodes. A three-layer perception neural network with in situ computing enabled was then constructed utilizing the proposed memristor and trained on the basis of the device's synaptic plasticity characteristics and conductance modulation rules. Recognition accuracies of 97.3% and 90% were achieved, respectively, for the raw and 20% noisy handwritten digits images from the Modified National Institute of Standards and Technology (MNIST) dataset, demonstrating the feasibility and applicability of implementing neuromorphic computing applications utilizing the proposed organic memristor.

Echo state graph neural networks with analogue random resistive memory arrays

Recent years have witnessed a surge of interest in learning representations of graph-structured data, with applications from social networks to drug discovery. However, graph neural networks, the machine learning models for handling graph-structured data, face significant challenges when running on conventional digital hardware, including the slowdown of Moore’s law due to transistor scaling limits and the von Neumann bottleneck incurred by physically separated memory and processing units, as well as a high training cost. Here we present a hardware–software co-design to address these challenges, by designing an echo state graph neural network based on random resistive memory arrays, which are built from low-cost, nanoscale and stackable resistors for efficient in-memory computing. This approach leverages the intrinsic stochasticity of dielectric breakdown in resistive switching to implement random projections in hardware for an echo state network that effectively minimizes the training complexity thanks to its fixed and random weights. The system demonstrates state-of-the-art performance on both graph classification using the MUTAG and COLLAB datasets and node classification using the CORA dataset, achieving 2.16×, 35.42× and 40.37× improvements in energy efficiency for a projected random resistive memory-based hybrid analogue–digital system over a state-of-the-art graphics processing unit and 99.35%, 99.99% and 91.40% reductions of backward pass complexity compared with conventional graph learning. The results point to a promising direction for next-generation artificial intelligence systems for graph learning.

Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks

Hardware-based neural networks (NNs) can provide a significant breakthrough in artificial intelligence applications due to their ability to extract features from unstructured data and learn from them. However, realizing complex NN models remains challenging because different tasks, such as feature extraction and classification, should be performed at different memory elements and arrays. This further increases the required number of memory arrays and chip size. Here, we propose a three-dimensional ferroelectric NAND (3D FeNAND) array for the area-efficient hardware implementation of NNs. Vector-matrix multiplication is successfully demonstrated using the integrated 3D FeNAND arrays, and excellent pattern classification is achieved. By allocating each array of vertical layers in 3D FeNAND as the hidden layer of NN, each layer can be used to perform different tasks, and the classification of color-mixed patterns is achieved. This work provides a practical strategy to realize high-performance and highly efficient NN systems by stacking computation components vertically.

Area-Efficient Mapping of Convolutional Neural Networks to Memristor Crossbars Using Sub-Image Partitioning

Memristor crossbars can be very useful for realizing edge-intelligence hardware, because the neural networks implemented by memristor crossbars can save significantly more computing energy and layout area than the conventional CMOS (complementary metal-oxide-semiconductor) digital circuits. One of the important operations used in neural networks is convolution. For performing the convolution by memristor crossbars, the full image should be partitioned into several sub-images. By doing so, each sub-image convolution can be mapped to small-size unit crossbars, of which the size should be defined as 128 × 128 or 256 × 256 to avoid the line resistance problem caused from large-size crossbars. In this paper, various convolution schemes with 3D, 2D, and 1D kernels are analyzed and compared in terms of neural network's performance and overlapping overhead. The neural network's simulation indicates that the 2D + 1D kernels can perform the sub-image convolution using a much smaller number of unit crossbars with less rate loss than the 3D kernels. When the CIFAR-10 dataset is tested, the mapping of sub-image convolution of 2D + 1D kernels to crossbars shows that the number of unit crossbars can be reduced almost by 90% and 95%, respectively, for 128 × 128 and 256 × 256 crossbars, compared with the 3D kernels. On the contrary, the rate loss of 2D + 1D kernels can be less than 2%. To improve the neural network's performance more, the 2D + 1D kernels can be combined with 3D kernels in one neural network. When the normalized ratio of 2D + 1D layers is around 0.5, the neural network's performance indicates very little rate loss compared to when the normalized ratio of 2D + 1D layers is zero. However, the number of unit crossbars for the normalized ratio = 0.5 can be reduced by half compared with that for the normalized ratio = 0.

Memristive Circuit Design of Brain-Like Emotional Learning and Generation

In this work, a bionic memristive circuit with the functions of emotional learning and generation is proposed, which can perform brain-like emotional learning and generation based on various types of input information. The proposed circuit is designed based on the brain emotional learning theory in the limbic system, which mainly includes three layers of design: 1) the bottom layer is the design of the basic unit modules, such as neuron and synapse; 2) the middle layer is the design of the functional modules related to emotional learning in the limbic system, such as the amygdala, thalamus, and so on; and 3) the top layer is the design of the overall circuit, which is used to realize the function of the emotional generation. A 2-D emotional space composed of valence and arousal signals is adopted. According to the above bottom-up circuit design method, the valence and arousal signals can be generated, respectively, by designing corresponding emotional learning circuits, so as to form continuous emotions. The volatile and nonvolatile memristors are mainly used to mimic the functions of the neuron and synapse at the bottom layer of the circuit to achieve the core emotional learning function of the middle layer, thereby constructing a brain-like information processing architecture to realize the function of the emotional generation in the top layer. The simulation results in PSPICE show that the proposed circuit can learn and generate emotions like humans. If the proposed circuit is applied to a humanoid robot platform through further research, the robot may have the ability of personalized emotional interaction with humans, so that it can be effectively used in emotional companionship and other aspects.

Analog Tunnel Memory Based on Programmable Metallization for Passive Neuromorphic Circuits

Although experimental implementations of memristive crossbar arrays have indicated the potential of these networks for in-memory computing, their performance is generally limited by an intrinsic variability on the device level as a result of the stochastic formation of conducting filaments. A tunnel-type memristive device typically exhibits small switching variations, owing to the relatively uniform interface effect. However, the low mobility of oxygen ions and large depolarization field result in slow operation speed and poor retention. Here, we demonstrate a quantum-tunneling memory with Ag-doped percolating systems, which possesses desired characteristics for large-scale artificial neural networks. The percolating layer suppresses the random formation of conductive filaments, and the nonvolatile modulation of the Fowler-Nordheim tunneling current is enabled by the collective movement of active Ag nanocrystals with high mobility and a minimal depolarization field. Such devices simultaneously possess electroforming-free characteristics, record low switching variabilities (temporal and spatial variation down to 1.6 and 2.1%, respectively), nanosecond operation speed, and long data retention (>10⁴ s at 85 °C). Simulations prove that passive arrays with our analog memory of large current-voltage nonlinearity achieve a high write and recognition accuracy. Thus, our discovery of the unique tunnel memory contributes to an important step toward realizing neuromorphic circuits.

Reservoir Computing-Based Design of ZnO Memristor-Type Digital Identification Circuits

Reservoir Computing (RC) is a network architecture inspired by biological neural systems that maps time-dimensional input features to a high-dimensional space for computation. The key to hardware implementation of the RC system is whether sufficient reservoir states can be generated. In this paper, a laboratory-prepared zinc oxide (ZnO) memristor is reported and modeled. The device is found to have nonlinear dynamic responses and characteristics of simulating neurosynaptic long-term potentiation (LTP) and long-term depression (LTD). Based on this, a novel two-level RC structure based on the ZnO memristor is proposed. Novel synaptic encoding is used to maintain stress activity based on the characteristics of after-discharge and proneness to fatigue during synaptic transmission. This greatly alleviates the limitations of the self-attenuating characteristic reservoir of the duration and interval of the input signal. This makes the reservoir, in combination with a fully connected neural network, an ideal system for time series classification. The experimental results show that the recognition rate for the complete MNIST dataset is 95.08% when 35 neurons are present as hidden layers while achieving low training consumption.

Digital Keying Enabled by Reconfigurable 2D Modulators

Energy, area, and bandwidth efficient communication primitives are essential to sustain the rapid increase in connectivity among internet-of-things (IoT) edge devices. While IoT edge-sensing, edge-computing, and edge-storage have witnessed innovation in materials and devices, IoT edge communication is yet to experience such transformation. The aging silicon (Si)-based complementary metal-oxide-semiconductor (CMOS) technology continues to remain the mainstay of communication devices where they are used to implement amplitude, frequency, and phase shift keying (amplitude-shift keying [ASK]/frequency-shift keying [FSK]/phase-shift keying [PSK]). Keying allows digital information to be communicated over a radio channel. While CMOS-based keying devices have evolved over the years, their hardware footprint and energy consumption are major concerns for resource constrained IoT communication. Furthermore, separate circuit designs and hardware elements are needed for each keying scheme and achieving multibit modulation to improve bandwidth efficiency remains a challenge. Here, a reconfigurable modulator is introduced that exploits unique ambipolar transport and programmable Dirac voltage in ultrathin MoTe₂ field-effect transistors to achieve ASK, FSK, and PSK modulation. Furthermore, by integrating two programmed MoTe₂ field-effect transistors, multibit data modulation is demonstrated, which improves the bandwidth efficiency by 200%. Finally, a frequency quadrupler is also realized exploiting the unique "double-well" transfer characteristic.