WSe2 Homojunction Devices: Electrostatically Configurable as Diodes, MOSFETs, and Tunnel FETs for Reconfigurable Computing

Content-Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing

As a promising alternative to the von Neumann architecture, in-memory computing holds the promise of delivering a high computing capacity while consuming low power. In this paper, we show that the ferroelectric reconfigurable transistor can serve as a versatile logic-in-memory unit that can perform logic operations and data storage concurrently. When functioning as memory, a ferroelectric reconfigurable transistor can implement content-addressable memory (CAM) with a 1-transistor-per-bit density. With the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM is realized in a single transistor, which can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multibit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and the stored entries. When functioning as a logic element, a ferroelectric reconfigurable transistor can be switched between n- and p-type modes. Utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real time without changing the layout, and the configuration is nonvolatile.

A review on advanced band-structure engineering with dynamic control for nonvolatile memory based 2D transistors

With advancements in information technology, an enormous amount of data is being generated that must be quickly accessible. However, conventional Si memory cells are approaching their physical limits and will be unable to meet the requirements of intense applications in the future. Notably, 2D atomically thin materials have demonstrated multiple novel physical and chemical properties that can be used to investigate next-generation electronic devices and breakthrough physical limits to continue Moore's law. Band structure is an important semiconductor parameter that determines their electrical and optical properties. In particular, 2D materials have highly tunable bandgaps and Fermi levels that can be achieved through band structure engineering methods such as heterostructure, substrate engineering, chemical doping, intercalation, and electrostatic doping. In particular, dynamic control of band structure engineering can be used in recent advancements in 2D devices to realize nonvolatile storage performance. This study examines recent advancements in 2D memory devices that utilize band structure engineering. The operational mechanisms and memory characteristics are described for each band structure engineering method. Band structure engineering provides a platform for developing new structures and realizing superior performance with respect to nonvolatile memory.

The floating body effect of a WSe2 transistor with volatile memory performance

The floating body effect in Meta-Stable-Dip RAM (MSDRAM) has been broadly employed in implementing single-transistor capacitor-less (1T0C) dynamic random access memory (DRAM) cells to break through the limitation of finite size reduction of peripheral capacitors. However, the majority of them were broadly demonstrated in conventional CMOS technology, while emerging semiconductor systems are rarely explored. Here, we creatively explore exfoliated multilayer tungsten diselenide (WSe₂) for the application of 1T0C DRAM, breaking the limitation of channel thickness in the traditional architecture. Through the comparison of the electrical characteristics among three dual-gate transistors with different lengths of top-gate, we demonstrated the essential role of the floating body effect in achieving the function of 1T0C DRAM displaying two distinct states that are differentiated by hole population within the floating body. Moreover, according to the analysis of in situ electrostatic force microscopy (EFM) measurements and theoretical calculation via density functional theory (DFT), the injection of holes through band-to-band (B2B) tunneling can be ascribed to the effectively electrostatic modulation. These consequences prove our innovative concept to achieve the function of 1T0C DRAM through employing the ML WSe₂, which is a vital step toward the breakthrough of the inherent limitations of DRAM cells.

Mobility Extraction in 2D Transition Metal Dichalcogenide Devices-Avoiding Contact Resistance Implicated Overestimation

Schottky barrier (SB) transistors operate distinctly different from conventional metal-oxide semiconductor field-effect transistors, in a unique way that the gate impacts the carrier injection from the metal source/drain contacts into the channel region. While it has been long recognized that this can have severe implications for device characteristics in the subthreshold region, impacts of contact gating of SB in the on-state of the devices, which affects evaluation of intrinsic channel properties, have been yet comprehensively studied. Due to the fact that contact resistance (R_C ) is always gate-dependent in a typical back-gated device structure, the traditional approach of deriving field-effect mobility from the maximum transconductance (g_m ) is in principle not correct and can even overestimate the mobility. In addition, an exhibition of two different threshold voltages for the channel and the contact region leads to another layer of complexity in determining the true carrier concentration calculated from Q = C_OX * (V_G -V_TH ). Through a detailed experimental analysis, the effect of different effective oxide thicknesses, distinct SB heights, and doping-induced reductions in the SB width are carefully evaluated to gain a better understanding of their impact on important device metrics.

Energy-efficient transistors: suppressing the subthreshold swing below the physical limit

With the miniaturization of silicon-based electronic components, power consumption is becoming a fundamental issue for micro-nano electronic circuits. The main reason for this is that the scaling of the supply voltage in the ultra-large-scale integrated circuit cannot keep up with the shrinking of the characteristic size of conventional transistors due to the physical limit termed "Boltzmann Tyranny", in which a gate voltage of at least 60 mV is required to modulate the drain current by one order of magnitude. Accordingly, to solve this problem, several new transistor architectures have been designed to reduce the subthreshold swing (SS) to lower than the fundamental limitation, thus lowering the supply voltage and reducing the power consumption. In this review, we first analytically formulate the SS, summarize the methods for reducing the SS, and propose four new transistor concepts, including tunnelling field-effect transistor, negative capacitance field-effect transistor, impact ionization field-effect transistor, and cold source field-effect transistor. Then, we review their physical mechanisms and optimization methods and consider the potential and drawbacks of these four new transistors. Finally, we discuss the challenges encountered in the investigation of these steep-slope transistors and present the future outlook.

2D Homojunctions for Electronics and Optoelectronics

In the post-Moore era, 2D materials with rich physical properties have attracted widespread attention from the scientific and industrial communities. Among 2D materials, the 2D homojunctions are of great promise in designing novel electronic and optoelectronic devices due to their unique geometries and properties such as homogeneous components, perfect lattice matching, and efficient charge transfer at the interface. In this article, a pioneering review focusing on the structural design and device application of 2D homojunctions such as p-n homojunctions, heterophase homojunctions, and layer-engineered homojunctions is provided. The preparation strategies to construct 2D homojunctions including vapor-phase deposition, lithium intercalation, laser irradiation, chemical doping, electrostatic doping, and photodoping are summarized in detail. Specifically, a careful review on the applications of the 2D homojunctions in electronics (e.g., field-effect transistors, rectifiers, and inverters) and optoelectronics (e.g., light-emitting diodes, photovoltaics, and photodetectors) is provided. Eventually, the current challenges and future perspectives are commented for promoting the rapid development of 2D homojunctions.