Fast Charge Sensing of Si/SiGe Quantum Dots via a High-Frequency Accumulation Gate

Dielectrics for Two-Dimensional Transition-Metal Dichalcogenide Applications

Despite over a decade of intense research efforts, the full potential of two-dimensional transition-metal dichalcogenides continues to be limited by major challenges. The lack of compatible and scalable dielectric materials and integration techniques restrict device performances and their commercial applications. Conventional dielectric integration techniques for bulk semiconductors are difficult to adapt for atomically thin two-dimensional materials. This review provides a brief introduction into various common and emerging dielectric synthesis and integration techniques and discusses their applicability for 2D transition metal dichalcogenides. Dielectric integration for various applications is reviewed in subsequent sections including nanoelectronics, optoelectronics, flexible electronics, valleytronics, biosensing, quantum information processing, and quantum sensing. For each application, we introduce basic device working principles, discuss the specific dielectric requirements, review current progress, present key challenges, and offer insights into future prospects and opportunities.

Designs for a two-dimensional Si quantum dot array with spin qubit addressability

Electron spins in Si are an attractive platform for quantum computation, backed with their scalability and fast, high-fidelity quantum logic gates. Despite the importance of two-dimensional integration with efficient connectivity between qubits for medium- to large-scale quantum computation, however, a practical device design that guarantees qubit addressability is yet to be seen. Here, we propose a practical 3 × 3 quantum dot device design and a larger-scale design as a longer-term target. The design goal is to realize qubit connectivity to the four nearest neighbors while ensuring addressability. We show that a 3 × 3 quantum dot array can execute four-qubit Grover’s algorithm more efficiently than the one-dimensional counterpart. To scale up the two-dimensional array beyond 3 × 3, we propose a novel structure with ferromagnetic gate electrodes. Our results showcase the possibility of medium-sized quantum processors in Si with fast quantum logic gates and long coherence times.

Single-electron operations in a foundry-fabricated array of quantum dots

Silicon quantum dots are attractive for the implementation of large spin-based quantum processors in part due to prospects of industrial foundry fabrication. However, the large effective mass associated with electrons in silicon traditionally limits single-electron operations to devices fabricated in customized academic clean rooms. Here, we demonstrate single-electron occupations in all four quantum dots of a 2 x 2 split-gate silicon device fabricated entirely by 300-mm-wafer foundry processes. By applying gate-voltage pulses while performing high-frequency reflectometry off one gate electrode, we perform single-electron operations within the array that demonstrate single-shot detection of electron tunneling and an overall adjustability of tunneling times by a global top gate electrode. Lastly, we use the two-dimensional aspect of the quantum dot array to exchange two electrons by spatial permutation, which may find applications in permutation-based quantum algorithms.

Radio-Frequency-Detected Fast Charge Sensing in Undoped Silicon Quantum Dots

Spin qubits in silicon quantum dots offer a promising platform for a quantum computer as they have a long coherence time and scalability. The charge sensing technique plays an essential role in reading out the spin qubit as well as tuning the device parameters, and therefore, its performance in terms of measurement bandwidth and sensitivity is an important factor in spin qubit experiments. Here we demonstrate fast and sensitive charge sensing by radio frequency reflectometry of an undoped, accumulation-mode Si/SiGe double quantum dot. We show that the large parasitic capacitance in typical accumulation-mode gate geometries impedes reflectometry measurements. We present a gate geometry that significantly reduces the parasitic capacitance and enables fast single-shot readout. The technique allows us to distinguish between the singly- and doubly occupied two-electron states under the Pauli spin blockade condition in an integration time of 0.8 μs, the shortest value ever reported in silicon, by the signal-to-noise ratio of 6. These results provide a guideline for designing silicon spin qubit devices suitable for the fast and high-fidelity readout.