Tunable Coupling and Isolation of Single Electrons in Silicon Metal-Oxide-Semiconductor Quantum Dots

Shared control of a 16 semiconductor quantum dot crossbar array

The efficient control of a large number of qubits is one of the most challenging aspects for practical quantum computing. Current approaches in solid-state quantum technology are based on brute-force methods, where each and every qubit requires at least one unique control line-an approach that will become unsustainable when scaling to the required millions of qubits. Here, inspired by random-access architectures in classical electronics, we introduce the shared control of semiconductor quantum dots to efficiently operate a two-dimensional crossbar array in planar germanium. We tune the entire array, comprising 16 quantum dots, to the few-hole regime. We then confine an odd number of holes in each site to isolate an unpaired spin per dot. Moving forward, we demonstrate on a vertical and a horizontal double quantum dot a method for the selective control of the interdot coupling and achieve a tunnel coupling tunability over more than 10 GHz. The operation of a quantum electronic device with fewer control terminals than tunable experimental parameters represents a compelling step forward in the construction of scalable quantum technology.

Tunable couplings between location-insensitive emitters mediated by an epsilon-near-zero plasmonic waveguide

This work demonstrates the efficient tuning of incoherent and coherent coupling between emitters embedded in an epsilon-near-zero (ENZ) waveguide coated with a multilayer graphene. As a result, a tunable two-qubit quantum phase gate based on the ENZ waveguide is realized at the cutoff frequency. Furthermore, due to the vanishingly small permittivity of the ENZ waveguide, all incoherent coupling between any two identical emitters located in the central area of the slit approaches a maximum, enabling near-ideal bipartite and multipartite entanglement. The coherent coupling between emitters is much larger at an operating frequency far from the ENZ resonance frequency than at the cutoff frequency, and the coherent coupling and resulting energy transfer efficiency can also be effectively tuned by the Fermi level of graphene. These results demonstrate an efficiently tunable electro-optical platform for quantum devices.

Combining n-MOS Charge Sensing with p-MOS Silicon Hole Double Quantum Dots in a CMOS platform

Holes in silicon quantum dots are receiving attention due to their potential as fast, tunable, and scalable qubits in semiconductor quantum circuits. Despite this, challenges remain in this material system including difficulties using charge sensing to determine the number of holes in a quantum dot, and in controlling the coupling between adjacent quantum dots. We address these problems by fabricating an ambipolar complementary metal-oxide-semiconductor (CMOS) device using multilayer palladium gates. The device consists of an electron charge sensor adjacent to a hole double quantum dot. We demonstrate control of the spin state via electric dipole spin resonance. We achieve smooth control of the interdot coupling rate over 1 order of magnitude and use the charge sensor to perform spin-to-charge conversion to measure the hole singlet-triplet relaxation time of 11 μs for a known hole occupation. These results provide a path toward improving the quality and controllability of hole spin-qubits.

Colloquium: Advances in automation of quantum dot devices control

Arrays of quantum dots (QDs) are a promising candidate system to realize scalable, coupled qubit systems and serve as a fundamental building block for quantum computers. In such semiconductor quantum systems, devices now have tens of individual electrostatic and dynamical voltages that must be carefully set to localize the system into the single-electron regime and to realize good qubit operational performance. The mapping of requisite QD locations and charges to gate voltages presents a challenging classical control problem. With an increasing number of QD qubits, the relevant parameter space grows sufficiently to make heuristic control unfeasible. In recent years, there has been considerable effort to automate device control that combines script-based algorithms with machine learning (ML) techniques. In this Colloquium, a comprehensive overview of the recent progress in the automation of QD device control is presented, with a particular emphasis on silicon- and GaAs-based QDs formed in two-dimensional electron gases. Combining physics-based modeling with modern numerical optimization and ML has proven effective in yielding efficient, scalable control. Further integration of theoretical, computational, and experimental efforts with computer science and ML holds vast potential in advancing semiconductor and other platforms for quantum computing.

Reduced Electron Temperature in Silicon Multi-Quantum-Dot Single-Electron Tunneling Devices

The high-performance room-temperature-operating Si single-electron transistors (SETs) were devised in the form of the multiple quantum-dot (MQD) multiple tunnel junction (MTJ) system. The key device architecture of the Si MQD MTJ system was self-formed along the volumetrically undulated [110] Si nanowire that was fabricated by isotropic wet etching and subsequent oxidation of the e-beam-lithographically patterned [110] Si nanowire. The strong subband modulation in the volumetrically undulated [110] Si nanowire could create both the large quantum level spacings and the high tunnel barriers in the Si MQD MTJ system. Such a device scheme can not only decrease the cotunneling effect, but also reduce the effective electron temperature. These eventually led to the energetic stability for both the Coulomb blockade and the negative differential conductance characteristics at room temperature. The results suggest that the present device scheme (i.e., [110] Si MQD MTJ) holds great promise for the room-temperature demonstration of the high-performance Si SETs.

A Flexible Design Platform for Si/SiGe Exchange-Only Qubits with Low Disorder

Spin-based silicon quantum dots are an attractive qubit technology for quantum information processing with respect to coherence time, control, and engineering. Here we present an exchange-only Si qubit device platform that combines the throughput of CMOS-like wafer processing with the versatility of direct-write lithography. The technology, which we coin "SLEDGE", features dot-shaped gates that are patterned simultaneously on one topographical plane and subsequently connected by vias to interconnect metal lines. The process design enables nontrivial layouts as well as flexibility in gate dimensions, material selection, and additional device features such as for rf qubit control. We show that the SLEDGE process has reduced electrostatic disorder with respect to traditional overlapping gate devices with lift-off metallization, and we present spin coherent exchange oscillations and single qubit blind randomized benchmarking data.

A High-Sensitivity Charge Sensor for Silicon Qubits above 1 K

Recent studies of silicon spin qubits at temperatures above 1 K are encouraging demonstrations that the cooling requirements for solid-state quantum computing can be considerably relaxed. However, qubit readout mechanisms that rely on charge sensing with a single-island single-electron transistor (SISET) quickly lose sensitivity due to thermal broadening of the electron distribution in the reservoirs. Here we exploit the tunneling between two quantized states in a double-island single-electron transistor (SET) to demonstrate a charge sensor with an improvement in the signal-to-noise ratio by an order of magnitude compared to a standard SISET, and a single-shot charge readout fidelity above 99% up to 8 K at a bandwidth greater than 100 kHz. These improvements are consistent with our theoretical modeling of the temperature-dependent current transport for both types of SETs. With minor additional hardware overhead, these sensors can be integrated into existing qubit architectures for a high-fidelity charge readout at few-kelvin temperatures.

Materials challenges and opportunities for quantum computing hardware

Quantum computing hardware technologies have advanced during the past two decades, with the goal of building systems that can solve problems that are intractable on classical computers. The ability to realize large-scale systems depends on major advances in materials science, materials engineering, and new fabrication techniques. We identify key materials challenges that currently limit progress in five quantum computing hardware platforms, propose how to tackle these problems, and discuss some new areas for exploration. Addressing these materials challenges will require scientists and engineers to work together to create new, interdisciplinary approaches beyond the current boundaries of the quantum computing field.

Probing hole spin transport of disorder quantum dots via Pauli spin-blockade in standard silicon transistors

Single hole transport and spin detection is achievable in standard p-type silicon transistors owing to the strong orbital quantization of disorder based quantum dots. Through the use of the well acting as a pseudo-gate, we discover the formation of a double-quantum dot system exhibiting Pauli spin-blockade and investigate the magnetic field dependence of the leakage current. This enables attributes that are key to hole spin state control to be determined, where we calculate a tunnel couplingt_cof 57μeV and a short spin-orbit lengthl_SOof 250 nm. The demonstrated strong spin-orbit interaction at the interface when using disorder based quantum dots supports electric-field mediated control. These results provide further motivation that a readily scalable platform such as industry standard silicon technology can be used to investigate interactions which are useful for quantum information processing.

Alternatives to aluminum gates for silicon quantum devices: defects and strain

Gate-defined quantum dots (QD) benefit from the use of small grain size metals for gate materials because it aids in shrinking the device dimensions. However, it is not clear what differences arise with respect to process-induced defect densities and inhomogeneous strain. Here, we present measurements of fixed charge, Q _f , interface trap density, D _it , the intrinsic film stress, σ, and the coefficient of thermal expansion, α as a function of forming gas anneal temperature for Al, Ti/Pd, and Ti/Pt gates. We show D _it is minimal at an anneal temperature of 350 °C for all materials but Ti/Pd and Ti/Pt have higher Q _f and D _it compared to Al. In addition, σ and α increase with anneal temperature for all three metals with α larger than the bulk value. These results indicate that there is a tradeoff between minimizing defects and minimizing the impact of strain in quantum device fabrication.

Developing Single Layer MOS Quantum Dots for Diagnostic Qubits

The design, fabrication and characterization of single metal gate layer, metal-oxide-semiconductor (MOS) quantum dot devices robust against dielectric breakdown are presented as prototypes for future diagnostic qubits. These devices were developed as a preliminary solution to a longer term goal of a qubit platform for intercomparison between materials or for in-line diagnostics, and to provide a testbed for establishing classical measurements predictive of coherence performance. For this stage, we seek a robust MOS design that is compatible with wafer and chip architectures, that has a reduced process overhead and is sufficiently capable of challenging and advancing our measurement capabilities. In this report, we present our initial batch of silicon MOS devices using a single gate layer, which have not exhibited any failures with gate voltage excursions > 10 V, but do exhibit the reduced electrostatic control expected of a single gate layer design. We observe quantum dot formation, capacitive charge sensing between channels, and reasonable effective electron temperatures that enable spin qubit studies. The costs and benefits of the trade-off between device performance and fabrication efficiency will be discussed, as well as opportunities for future improvements.

Universal quantum logic in hot silicon qubits

Quantum computation requires many qubits that can be coherently controlled and coupled to each other¹. Qubits that are defined using lithographic techniques have been suggested to enable the development of scalable quantum systems because they can be implemented using semiconductor fabrication technology^2-5. However, leading solid-state approaches function only at temperatures below 100 millikelvin, where cooling power is extremely limited, and this severely affects the prospects of practical quantum computation. Recent studies of electron spins in silicon have made progress towards a platform that can be operated at higher temperatures by demonstrating long spin lifetimes⁶, gate-based spin readout⁷ and coherent single-spin control⁸. However, a high-temperature two-qubit logic gate has not yet been demonstrated. Here we show that silicon quantum dots can have sufficient thermal robustness to enable the execution of a universal gate set at temperatures greater than one kelvin. We obtain single-qubit control via electron spin resonance and readout using Pauli spin blockade. In addition, we show individual coherent control of two qubits and measure single-qubit fidelities of up to 99.3 per cent. We demonstrate the tunability of the exchange interaction between the two spins from 0.5 to 18 megahertz and use it to execute coherent two-qubit controlled rotations. The demonstration of 'hot' and universal quantum logic in a semiconductor platform paves the way for quantum integrated circuits that host both the quantum hardware and its control circuitry on the same chip, providing a scalable approach towards practical quantum information processing.