Modulation of Binary Neuroplasticity in a Heterojunction-Based Ambipolar Transistor

Multifunctional In-Memory Logics Based on a Dual-Gate Antiambipolar Transistor toward Non-von Neumann Computing Architecture

In-memory computing may make it possible to realize non-von Neumann computing because the logic circuits are unified in the memory units. We investigated two types of in-memory logic operations, namely, two-input logic circuits and multifunctional artificial synapses. These were realized in a dual-gate antiambipolar transistor (AAT) with a ReS2/WSe2 heterojunction, in which polystyrene with a zinc phthalocyanine core (ZnPc-PS4) was incorporated as a memory layer. Here, reconfigurability is a key concept for both types of device operations and was achieved by merging the Λ-shaped transfer curve of the AAT and the nonvolatile memory effect of ZnPc-PS4. First, we achieved electrically reconfigurable two-input logic circuits. Versatile logic circuits such as AND, OR, NAND, NOR, and XOR circuits were demonstrated by taking advantage of the Λ-shaped transfer curve of the dual-gate AAT. Importantly, the nonvolatile memory function provided the electrical switching of the individual circuits between AND/OR, NAND/NOR, and XOR/NAND circuits with constant input signals. Second, the memory effect was applied to multifunctional artificial synapses. The inhibitory/excitatory and long-term potentiation/depression synaptic operations were electrically reconfigured simply by controlling one parameter (readout voltage), making three distinct responses possible even with the same presynaptic signals. These findings provide hints that may lead to the realization of new in-memory computing architectures beyond the current von Neumann computers.

Flexible and Energy-Efficient Synaptic Transistor with Quasi-Linear Weight Update Protocol by Inkjet Printing of Orientated Polar-Electret/High-k Oxide Composite Dielectric

Inkjet printing artificial synapse is cost-effective but challenging in emulating synaptic dynamics with a sufficient number of effective weight states under ultralow voltage spiking operation. A synaptic transistor gated by inkjet-printed composite dielectric of polar-electret polyvinylpyrrolidone (PVP) and high-k zirconia oxide (ZrOx) is proposed and thus synthesized to solve this issue. Quasi-linear weight update with a large variation margin is obtained through the coupling effect and the facilitation of dipole orientation, which can be attributed to the orderly arranged molecule chains induced by the carefully designed microfluidic flows. Crucial features of biological synapses including long-term plasticity, spike-timing-dependence-plasticity (STDP), "Learning-Experience" behavior, and ultralow energy consumption (<10 fJ/pulse) are successfully implemented on the device. Simulation results exhibit an excellent image recognition accuracy (97.1%) after 15 training epochs, which is the highest for printed synaptic transistors. Moreover, the device sustained excellent endurance against bending tests with radius down to 8 mm. This work presents a very viable solution for constructing the futuristic flexible and low-cost neural systems.

Toward grouped-reservoir computing: organic neuromorphic vertical transistor with distributed reservoir states for efficient recognition and prediction

Reservoir computing has attracted considerable attention due to its low training cost. However, existing neuromorphic hardware, focusing mainly on shallow-reservoir computing, faces challenges in providing adequate spatial and temporal scales characteristic for effective computing. Here, we report an ultra-short channel organic neuromorphic vertical transistor with distributed reservoir states. The carrier dynamics used to map signals are enriched by coupled multivariate physics mechanisms, while the vertical architecture employed greatly increases the feedback intensity of the device. Consequently, the device as a reservoir, effectively mapping sequential signals into distributed reservoir state space with 1152 reservoir states, and the range ratio of temporal and spatial characteristics can simultaneously reach 2640 and 650, respectively. The grouped-reservoir computing based on the device can simultaneously adapt to different spatiotemporal task, achieving recognition accuracy over 94% and prediction correlation over 95%. This work proposes a new strategy for developing high-performance reservoir computing networks.

Mixed-Dimensional Nanoparticle-Nanowire Channels for Flexible Optoelectronic Artificial Synapse with Enhanced Photoelectric Response and Asymmetric Bidirectional Plasticity

A mixed-dimensional dual-channel synaptic transistor composed of inorganic nanoparticles and organic nanowires was fabricated to expand the photoelectric gain range. The device can actualize the sensitization features of the nociceptor and shows improved responsiveness to visible light. Under electrical pulses with different polarities, the apparatus exhibits reconfigurable asymmetric bidirectional plasticity. Moreover, the devices demonstrate good operational tolerance and mechanical stability, retaining more than 60% of their maximum responsiveness after 100 consecutive/bidirectional and 1000 flex/flat operations. The improved photoelectric response of the device endows a high image recognition accuracy of greater than 80%. Asymmetric bidirectional plasticity is used as punishment/reward in a psychological experiment to emulate the improvement of learning motivation and enables real-time forward and backward deflection (+7 and -25°) of artificial muscle. The mixed-dimensional optoelectronic artificial synapses with switchable behavior and electron/hole transport type have important prospects for neuromorphic processing and artificial somatosensory nerves.

Enhanced Synaptic Behaviors in Chitosan Electrolyte-Based Electric-Double-Layer Transistors with Poly-Si Nanowire Channel Structures

In this study, we enhance the synaptic behavior of artificial synaptic transistors by utilizing nanowire (NW)-type polysilicon channel structures. The high surface-to-volume ratio of the NW channels enables efficient modulation of the channel conductance, which is interpreted as the synaptic weight. As a result, NW-type synaptic transistors exhibit a larger hysteresis window compared to film-type synaptic transistors, even within the same gate voltage sweeping range. Moreover, NW-type synaptic transistors demonstrate superior short-term facilitation and long-term memory transition compared with film-type ones, as evidenced by the measured paired-pulse facilitation and excitatory post-synaptic current characteristics at varying frequencies and pulse numbers. Additionally, we observed gradual potentiation/depression characteristics, making these artificial synapses applicable to artificial neural networks. Furthermore, the NW-type synaptic transistors exhibit improved Modified National Institute of Standards and Technology pattern recognition rate of 91.2%. In conclusion, NW structure channels are expected to be a promising technology for next-generation artificial intelligence (AI) semiconductors, and the integration of NW structure channels has significant potential to advance AI semiconductor technology.

Reconfigurable Artificial Synapse Based on Ambipolar Floating Gate Memory

Artificial synapse networks capable of massively parallel computing and mimicking biological neural networks can potentially improve the processing efficiency of existing information technologies. Semiconductor devices functioning as excitatory and inhibitory synapses are crucial for developing intelligence systems, such as traffic control systems. However, achieving reconfigurability between two working modes (inhibitory and excitatory) and bilingual synaptic behavior in a single transistor remains challenging. This study successfully mimics a bilingual synaptic response using an artificial synapse based on an ambipolar floating gate memory comprising tungsten selenide (WSe₂)/hexagonal boron nitride (h-BN)/ molybdenum telluride (MoTe₂). In this WSe₂/h-BN/MoTe₂ structure, ambipolar semiconductors WSe₂ and MoTe₂ are inserted as channel and floating gates, respectively, and h-BN serves as the tunneling barrier layer. Using either positive or negative pulse amplitude modulations at the control gate, this device with bipolar channel conduction produced eight distinct resistance states. Based on this, we experimentally projected that we could achieve 490 memory states (210 hole-resistance states + 280 electron-resistance states). Using the bipolar charge transport and multistorage states of WSe₂/h-BN/MoTe₂ floating gate memory, we mimicked reconfigurable excitatory and inhibitory synaptic plasticity in a single device. Furthermore, the convolution neural network formed by these synaptic devices can recognize handwritten digits with an accuracy of >92%. This study identifies the unique properties of heterostructure devices based on two-dimensional materials as well as predicts their applicability in advanced recognition of neuromorphic computing.

Biological function simulation in neuromorphic devices: from synapse and neuron to behavior

As the boom of data storage and processing, brain-inspired computing provides an effective approach to solve the current problem. Various emerging materials and devices have been reported to promote the development of neuromorphic computing. Thereinto, the neuromorphic device represented by memristor has attracted extensive research due to its outstanding property to emulate the brain's functions from synaptic plasticity, sensory-memory neurons to some intelligent behaviors of living creatures. Herein, we mainly review the progress of these brain functions mimicked by neuromorphic devices, concentrating on synapse (i.e. various synaptic plasticity trigger by electricity and/or light), neurons (including the various sensory nervous system) and intelligent behaviors (such as conditioned reflex represented by Pavlov's dog experiment). Finally, some challenges and prospects related to neuromorphic devices are presented.

Binary-Synaptic Plasticity in Ambipolar Ni-Silicide Schottky Barrier Poly-Si Thin Film Transistors Using Chitosan Electric Double Layer

We propose an ambipolar chitosan synaptic transistor that effectively responds to binary neuroplasticity. We fabricated the synaptic transistors by applying a chitosan electric double layer (EDL) to the gate insulator of the excimer laser annealed polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Ni-silicide (NiSi) Schottky-barrier source/drain (S/D) junction. The undoped poly-Si channel and the NiSi S/D contact allowed conduction by electrons and holes, resulting in artificial synaptic behavior in both p-type and n-type regions. A slow polarization reaction by the mobile ions such as anions (CH₃COO^- and OH^-) and cations (H⁺) in the chitosan EDL induced hysteresis window in the transfer characteristics of the ambipolar TFTs. We demonstrated the excitatory post-synaptic current modulations and stable conductance modulation through repetitive potentiation and depression pulse. We expect the proposed ambipolar chitosan synaptic transistor that responds effectively to both positive and negative stimulation signals to provide more complex information process versatility for bio-inspired neuromorphic computing systems.

Carbon Nanotube-Based Flexible Ferroelectric Synaptic Transistors for Neuromorphic Computing

Biological nervous systems evolved in nature have marvelous information processing capacities, which have great reference value for modern information technologies. To expand the function of electronic devices with applications in smart health monitoring and treatment, wearable energy-efficient computing, neuroprosthetics, etc., flexible artificial synapses for neuromorphic computing will play a crucial role. Here, carbon nanotube-based ferroelectric synaptic transistors are realized on ultrathin flexible substrates via a low-temperature approach not exceeding 90 °C to grow ferroelectric dielectrics in which the single-pulse, paired-pulse, and repetitive-pulse responses testify to well-mimicked plasticity in artificial synapses. The long-term potentiation and long-term depression processes in the device demonstrate a dynamic range as large as 2000×, and 360 distinguishable conductance states are achieved with a weight increase/decrease nonlinearity of no more than 1 by applying stepped identical pulses. The stability of the device is verified by the almost unchanged performance after the device is kept in ambient conditions without additional passivation for 240 days. An artificial neural network-based simulation is conducted to benchmark the hardware performance of the neuromorphic devices in which a pattern recognition accuracy of 95.24% is achieved.

Ecofriendly Solution-Combustion-Processed Thin-Film Transistors for Synaptic Emulation and Neuromorphic Computing

The ecofriendly combustion synthesis (ECS) and self-combustion synthesis (ESCS) have been successfully utilized to deposit high-k aluminum oxide (AlO_x) dielectrics at low temperatures and applied for aqueous In₂O₃ thin-film transistors (TFTs) accordingly. The ECS and ESCS processes facilitate the formation of high-quality dielectrics at lower temperatures compared to conventional methods based on an ethanol precursor, as confirmed by thermal analysis and chemical composition characterization. The aqueous In₂O₃ TFTs based on ECS and ESCS-AlO_x show enhanced electrical characteristics and counterclockwise transfer-curve hysteresis. The memory-like counterclockwise behavior in the transfer curve modulated by the gate bias voltage is comparable to the signal modulation by the neurotransmitters. ECS and ESCS transistors are employed to perform synaptic emulation; various short-term and long-term memory functions are emulated with low operating voltages and high excitatory postsynaptic current levels. High stability and reproducibility are achieved within 240 pulses of long-term synaptic potentiation and depression. The synaptic emulation functions achieved in this work match the demand for artificial neural networks (ANN), and a multilayer perceptron (MLP) is developed using an ECS-AlO_x synaptic transistor for image recognition. A superior recognition rate of over 90% is achieved based on ECS-AlO_x synaptic transistors, which facilitates the implementation of the metal-oxide synaptic transistor for future neuromorphic computing via an ecofriendly route.

Large-Scale and Flexible Optical Synapses for Neuromorphic Computing and Integrated Visible Information Sensing Memory Processing

Optoelectronic synapses integrating synaptic and optical-sensing functions exhibit large advantages in neuromorphic computing for visual information processing and complex learning, recognition, and memory in an energy-efficient way. However, electric stimulation is still essential for existing optoelectronic synapses to realize bidirectional weight-updating, restricting the processing speed, bandwidth, and integration density of the devices. Herein, a two-terminal optical synapse based on a wafer-scale pyrenyl graphdiyne/graphene/PbS quantum dot heterostructure is proposed that can emulate both the excitatory and inhibitory synaptic behaviors in an optical pathway. The simple device architecture and low-dimensional features of the heterostructure endow the optical synapse with robust flexibility for wearable electronics. This optical synapse features a linear and symmetric conductance-update trajectory with numerous conductance states and low noise, which facilitates the demonstration of accurate and effective pattern recognition with a strong fault-tolerant capability even at bending states. A series of logic functions and associative learning capabilities have been demonstrated by the optical synapses in optical pathways, significantly enhancing the information processing capability for neuromorphic computing. Moreover, an integrated visible information sensing memory processing system based on the optical synapse array is constructed to perform real-time detection, in situ image memorization, and distinction tasks. This work is an important step toward the development of optogenetics-inspired neuromorphic computing and adaptive parallel processing networks for wearable electronics.

Channel Length-Dependent Operation of Ambipolar Schottky-Barrier Transistors on a Single Si Nanowire

For use in flexible, printable, wearable electronics, Schottky-barrier field-effect transistors (SB-FETs) with various channel materials including low-dimensional nanomaterials have been considered so far due to their comparatively simple and cost-effective integration scheme free of junction and channel dopants. However, the electric conduction mechanism and the scaling properties underlying their performance differ significantly from those of conventional metal-oxide-semiconductor (MOS) field-effect transistors. Indeed, an understanding of channel length scaling and drain bias impact has not been elucidated sufficiently. Here, multiple ambipolar SB-FETs with different channel lengths have been fabricated on a single silicon nanowire ensuring a constant nanowire diameter. Their length scaling behavior is analyzed through drain current and transconductance contour maps, each depending on the drain and gate bias. The reduced gate control and extended drain field effect on Schottky junctions were observed in short channels. Activation energy measurements showed lower sensitive behavior of the Schottky barrier to gate bias in the short-channel device and confirmed the thinning of Schottky barrier width for electrons at the source interface with drain bias.