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Radamson HH, Miao Y, Zhou Z, Wu Z, Kong Z, Gao J, Yang H, Ren Y, Zhang Y, Shi J, Xiang J, Cui H, Lu B, Li J, Liu J, Lin H, Xu H, Li M, Cao J, He C, Duan X, Zhao X, Su J, Du Y, Yu J, Wu Y, Jiang M, Liang D, Li B, Dong Y, Wang G. CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology. NANOMATERIALS (BASEL, SWITZERLAND) 2024; 14:837. [PMID: 38786792 PMCID: PMC11123950 DOI: 10.3390/nano14100837] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Key Words] [Grants] [Track Full Text] [Subscribe] [Scholar Register] [Received: 03/19/2024] [Revised: 04/24/2024] [Accepted: 04/29/2024] [Indexed: 05/25/2024]
Abstract
After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.
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Affiliation(s)
- Henry H. Radamson
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China; (Z.Z.); (Y.R.); (H.L.); (J.C.); (C.H.); (X.D.); (Y.W.); (B.L.)
| | - Yuanhao Miao
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China; (Z.Z.); (Y.R.); (H.L.); (J.C.); (C.H.); (X.D.); (Y.W.); (B.L.)
| | - Ziwei Zhou
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China; (Z.Z.); (Y.R.); (H.L.); (J.C.); (C.H.); (X.D.); (Y.W.); (B.L.)
| | - Zhenhua Wu
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
| | - Zhenzhen Kong
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
| | - Jianfeng Gao
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
| | - Hong Yang
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
| | - Yuhui Ren
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China; (Z.Z.); (Y.R.); (H.L.); (J.C.); (C.H.); (X.D.); (Y.W.); (B.L.)
| | - Yongkui Zhang
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
| | - Jiangliu Shi
- Beijing Superstring Academy of Memory Technology, Beijing 100176, China; (J.S.); (J.X.); (M.J.); (D.L.)
| | - Jinjuan Xiang
- Beijing Superstring Academy of Memory Technology, Beijing 100176, China; (J.S.); (J.X.); (M.J.); (D.L.)
| | - Hushan Cui
- Jiangsu Leuven Instruments Co., Ltd., Xuzhou 221300, China;
| | - Bin Lu
- School of Physics and Information Engineering, Shanxi Normal University, Linfen 041004, China;
| | - Junjie Li
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
| | - Jinbiao Liu
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
| | - Hongxiao Lin
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China; (Z.Z.); (Y.R.); (H.L.); (J.C.); (C.H.); (X.D.); (Y.W.); (B.L.)
| | - Haoqing Xu
- Institute of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China;
| | - Mengfan Li
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
- Institute of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China;
| | - Jiaji Cao
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China; (Z.Z.); (Y.R.); (H.L.); (J.C.); (C.H.); (X.D.); (Y.W.); (B.L.)
| | - Chuangqi He
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China; (Z.Z.); (Y.R.); (H.L.); (J.C.); (C.H.); (X.D.); (Y.W.); (B.L.)
| | - Xiangyan Duan
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China; (Z.Z.); (Y.R.); (H.L.); (J.C.); (C.H.); (X.D.); (Y.W.); (B.L.)
| | - Xuewei Zhao
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
- Institute of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China;
| | - Jiale Su
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
| | - Yong Du
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
| | - Jiahan Yu
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
| | - Yuanyuan Wu
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China; (Z.Z.); (Y.R.); (H.L.); (J.C.); (C.H.); (X.D.); (Y.W.); (B.L.)
| | - Miao Jiang
- Beijing Superstring Academy of Memory Technology, Beijing 100176, China; (J.S.); (J.X.); (M.J.); (D.L.)
| | - Di Liang
- Beijing Superstring Academy of Memory Technology, Beijing 100176, China; (J.S.); (J.X.); (M.J.); (D.L.)
| | - Ben Li
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China; (Z.Z.); (Y.R.); (H.L.); (J.C.); (C.H.); (X.D.); (Y.W.); (B.L.)
| | - Yan Dong
- Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (Z.W.); (Z.K.); (J.G.); (H.Y.); (Y.Z.); (J.L.); (J.L.); (M.L.); (X.Z.); (J.S.); (Y.D.); (J.Y.); (Y.D.)
| | - Guilei Wang
- Beijing Superstring Academy of Memory Technology, Beijing 100176, China; (J.S.); (J.X.); (M.J.); (D.L.)
- Hefei National Laboratory, University of Science and Technology of China, Hefei 230088, China
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Menon H, Jeddi H, Morgan NP, Fontcuberta I Morral A, Pettersson H, Borg M. Monolithic InSb nanostructure photodetectors on Si using rapid melt growth. NANOSCALE ADVANCES 2023; 5:1152-1162. [PMID: 36798495 PMCID: PMC9926903 DOI: 10.1039/d2na00903j] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Grants] [Track Full Text] [Figures] [Subscribe] [Scholar Register] [Received: 12/09/2022] [Accepted: 01/18/2023] [Indexed: 06/18/2023]
Abstract
Monolithic integration of InSb on Si could be a key enabler for future electronic and optoelectronic applications. In this work, we report the fabrication of InSb metal-semiconductor-metal photodetectors directly on Si using a CMOS-compatible process known as rapid melt growth. Fourier transform spectroscopy demonstrates a spectrally resolved photocurrent peak from a single crystalline InSb nanostructure with dimensions of 500 nm × 1.1 μm × 120 nm. Time-dependent optical characterization of a device under 1550 nm illumination indicated a stable photoresponse with responsivity of 0.50 A W-1 at 16 nW illumination, with a time constant in the range of milliseconds. Electron backscatter diffraction spectroscopy revealed that the single crystalline InSb nanostructures contain occasional twin defects and crystal lattice twist around the growth axis, in addition to residual strain, possibly causing the observation of a low-energy tail in the detector response extending the photosensitivity out to 10 μm wavelengths (0.12 eV) at 77 K.
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Affiliation(s)
- Heera Menon
- Electrical and Information Technology, Lund University Lund Sweden
- NanoLund, Lund University Box 118 Lund SE-221 00 Sweden
| | - Hossein Jeddi
- NanoLund, Lund University Box 118 Lund SE-221 00 Sweden
- School of Information Technology, Halmstad University Box 823 Halmstad SE-301 18 Sweden
- Solid State Physics, Lund University Box 118 Lund SE-221 00 Sweden
| | - Nicholas Paul Morgan
- Laboratory of Semiconductor Materials, Ecole Polytechnique Federale de Lausanne Lausanne Switzerland
| | - Anna Fontcuberta I Morral
- Laboratory of Semiconductor Materials, Ecole Polytechnique Federale de Lausanne Lausanne Switzerland
| | - Håkan Pettersson
- NanoLund, Lund University Box 118 Lund SE-221 00 Sweden
- School of Information Technology, Halmstad University Box 823 Halmstad SE-301 18 Sweden
- Solid State Physics, Lund University Box 118 Lund SE-221 00 Sweden
| | - Mattias Borg
- Electrical and Information Technology, Lund University Lund Sweden
- NanoLund, Lund University Box 118 Lund SE-221 00 Sweden
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Du Y, Xu B, Wang G, Miao Y, Li B, Kong Z, Dong Y, Wang W, Radamson HH. Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon. NANOMATERIALS 2022; 12:nano12050741. [PMID: 35269230 PMCID: PMC8912022 DOI: 10.3390/nano12050741] [Citation(s) in RCA: 10] [Impact Index Per Article: 5.0] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Download PDF] [Figures] [Subscribe] [Scholar Register] [Received: 12/22/2021] [Revised: 02/11/2022] [Accepted: 02/17/2022] [Indexed: 02/04/2023]
Abstract
Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized.
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Affiliation(s)
- Yong Du
- Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (B.X.); (G.W.); (Z.K.); (Y.D.); (W.W.)
- Correspondence: (Y.D.); (Y.M.); (H.H.R.); Tel.: +86-010-8299-5793 (Y.D.)
| | - Buqing Xu
- Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (B.X.); (G.W.); (Z.K.); (Y.D.); (W.W.)
- Institute of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China
| | - Guilei Wang
- Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (B.X.); (G.W.); (Z.K.); (Y.D.); (W.W.)
| | - Yuanhao Miao
- Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (B.X.); (G.W.); (Z.K.); (Y.D.); (W.W.)
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China;
- Correspondence: (Y.D.); (Y.M.); (H.H.R.); Tel.: +86-010-8299-5793 (Y.D.)
| | - Ben Li
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China;
| | - Zhenzhen Kong
- Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (B.X.); (G.W.); (Z.K.); (Y.D.); (W.W.)
- Institute of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China
| | - Yan Dong
- Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (B.X.); (G.W.); (Z.K.); (Y.D.); (W.W.)
| | - Wenwu Wang
- Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (B.X.); (G.W.); (Z.K.); (Y.D.); (W.W.)
- Institute of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China
| | - Henry H. Radamson
- Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; (B.X.); (G.W.); (Z.K.); (Y.D.); (W.W.)
- Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China;
- Department of Electronics Design, Mid Sweden University, Holmgatan 10, 85170 Sundsvall, Sweden
- Correspondence: (Y.D.); (Y.M.); (H.H.R.); Tel.: +86-010-8299-5793 (Y.D.)
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Wen P, Tiwari P, Mauthe S, Schmid H, Sousa M, Scherrer M, Baumann M, Bitachon BI, Leuthold J, Gotsmann B, Moselund KE. Waveguide coupled III-V photodiodes monolithically integrated on Si. Nat Commun 2022; 13:909. [PMID: 35177604 PMCID: PMC8854727 DOI: 10.1038/s41467-022-28502-6] [Citation(s) in RCA: 2] [Impact Index Per Article: 1.0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 06/21/2021] [Accepted: 01/14/2022] [Indexed: 11/10/2022] Open
Abstract
The seamless integration of III-V nanostructures on silicon is a long-standing goal and an important step towards integrated optical links. In the present work, we demonstrate scaled and waveguide coupled III-V photodiodes monolithically integrated on Si, implemented as InP/In0.5Ga0.5As/InP p-i-n heterostructures. The waveguide coupled devices show a dark current down to 0.048 A/cm2 at -1 V and a responsivity up to 0.2 A/W at -2 V. Using grating couplers centered around 1320 nm, we demonstrate high-speed detection with a cutoff frequency f3dB exceeding 70 GHz and data reception at 50 GBd with OOK and 4PAM. When operated in forward bias as a light emitting diode, the devices emit light centered at 1550 nm. Furthermore, we also investigate the self-heating of the devices using scanning thermal microscopy and find a temperature increase of only ~15 K during the device operation as emitter, in accordance with thermal simulation results.
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Affiliation(s)
- Pengyan Wen
- IBM Research Europe - Zurich, Säumerstrasse 4, 8803, Rüschlikon, Switzerland
| | - Preksha Tiwari
- IBM Research Europe - Zurich, Säumerstrasse 4, 8803, Rüschlikon, Switzerland
| | - Svenja Mauthe
- IBM Research Europe - Zurich, Säumerstrasse 4, 8803, Rüschlikon, Switzerland
| | - Heinz Schmid
- IBM Research Europe - Zurich, Säumerstrasse 4, 8803, Rüschlikon, Switzerland
| | - Marilyne Sousa
- IBM Research Europe - Zurich, Säumerstrasse 4, 8803, Rüschlikon, Switzerland
| | - Markus Scherrer
- IBM Research Europe - Zurich, Säumerstrasse 4, 8803, Rüschlikon, Switzerland
| | - Michael Baumann
- ETH Zürich, Institute of Electromagnetic Fields (IEF), Gloriastrasse 35, 8092, Zürich, Switzerland
| | - Bertold Ian Bitachon
- ETH Zürich, Institute of Electromagnetic Fields (IEF), Gloriastrasse 35, 8092, Zürich, Switzerland
| | - Juerg Leuthold
- ETH Zürich, Institute of Electromagnetic Fields (IEF), Gloriastrasse 35, 8092, Zürich, Switzerland
| | - Bernd Gotsmann
- IBM Research Europe - Zurich, Säumerstrasse 4, 8803, Rüschlikon, Switzerland
| | - Kirsten E Moselund
- IBM Research Europe - Zurich, Säumerstrasse 4, 8803, Rüschlikon, Switzerland.
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Zhu Z, Jönsson A, Liu YP, Svensson J, Timm R, Wernersson LE. Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si. ACS APPLIED ELECTRONIC MATERIALS 2022; 4:531-538. [PMID: 35098137 PMCID: PMC8793030 DOI: 10.1021/acsaelm.1c01134] [Citation(s) in RCA: 1] [Impact Index Per Article: 0.5] [Reference Citation Analysis] [Abstract] [Key Words] [Grants] [Track Full Text] [Subscribe] [Scholar Register] [Received: 11/15/2021] [Accepted: 12/30/2021] [Indexed: 05/17/2023]
Abstract
Sb-based semiconductors are critical p-channel materials for III-V complementary metal oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is typically inhibited by the low quality of the channel to gate dielectric interface, which leads to poor gate modulation. In this study, we achieve improved electrostatics of vertical GaSb nanowire p-channel MOSFETs by employing robust digital etch (DE) schemes, prior to high-κ deposition. Two different processes, based on buffer-oxide etcher (BOE) 30:1 and HCl:IPA 1:10, are compared. We demonstrate that water-based BOE 30:1, which is a common etchant in Si-based CMOS process, gives an equally controllable etching for GaSb nanowires compared to alcohol-based HCl:IPA, thereby realizing III-V on Si with the same etchant selection. Both DE chemicals show good interface quality of GaSb with a substantial reduction in Sb oxides for both etchants while the HCl:IPA resulted in a stronger reduction in the Ga oxides, as determined by X-ray photoelectron spectroscopy and in agreement with the electrical characterization. By implementing these DE schemes into vertical GaSb nanowire MOSFETs, a subthreshold swing of 107 mV/dec is obtained in the HCl:IPA pretreated sample, which is state of the art compared to reported Sb-based MOSFETs, suggesting a potential of Sb-based p-type devices for all-III-V CMOS technologies.
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Affiliation(s)
- Zhongyunshen Zhu
- Division
of Electromagnetics and Nanoelectronics, Department of Electrical
and Information Technology, Lund University, P.O. Box 117, 221 00 Lund, Sweden
| | - Adam Jönsson
- Division
of Electromagnetics and Nanoelectronics, Department of Electrical
and Information Technology, Lund University, P.O. Box 117, 221 00 Lund, Sweden
| | - Yen-Po Liu
- Division
of Synchrotron Radiation Research, Department of Physics, and NanoLund, Lund University, P.O.
Box 117, 221 00 Lund, Sweden
| | - Johannes Svensson
- Division
of Electromagnetics and Nanoelectronics, Department of Electrical
and Information Technology, Lund University, P.O. Box 117, 221 00 Lund, Sweden
| | - Rainer Timm
- Division
of Synchrotron Radiation Research, Department of Physics, and NanoLund, Lund University, P.O.
Box 117, 221 00 Lund, Sweden
| | - Lars-Erik Wernersson
- Division
of Electromagnetics and Nanoelectronics, Department of Electrical
and Information Technology, Lund University, P.O. Box 117, 221 00 Lund, Sweden
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Zhu Z, Svensson J, Jönsson A, Wernersson LE. Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing. NANOTECHNOLOGY 2021; 33:075202. [PMID: 34736238 DOI: 10.1088/1361-6528/ac3689] [Citation(s) in RCA: 1] [Impact Index Per Article: 0.3] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Received: 08/09/2021] [Accepted: 11/04/2021] [Indexed: 06/13/2023]
Abstract
GaSb is considered as an attractive p-type channel material for future III-V metal-oxide-semiconductor (MOS) technologies, but the processing conditions to utilize the full device potential such as low power logic applications and RF applications still need attention. In this work, applying rapid thermal annealing (RTA) to nanoscale GaSb vertical nanowire p-type MOS field-effect transistors, we have improved the average peak transconductance (gm,peak) by 50% among 28 devices and achieved 70μSμm-1atVDS = -0.5 V in a device with 200 nm gate length. In addition, a low subthreshold swing down to 144 mV dec-1as well as an off-current below 5 nAμm-1which refers to the off-current specification in low-operation-power condition has been obtained. Based on the statistical analysis, the results show a great enhancement in both on- and off-state performance with respect to previous work mainly due to the improved electrostatics and contacts after RTA, leading to a potential in low-power logic applications. We have also examined a short channel device withLg = 80 nm in RTA, which shows an increasedgm,peakup to 149μSμm-1atVDS = -0.5 V as well as a low on-resistance of 4.7 kΩ·μm. The potential of further enhancement ingmvia RTA offers a good alternative to obtain high-performance devices for RF applications which have less stringent requirement for off-state performance. Our results indicate that post-fabrication annealing provides a great option to improve the performance of GaSb-based p-type devices with different structures for various applications.
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Affiliation(s)
- Zhongyunshen Zhu
- Division of Electromagnetics and Nanoelectronics, Department of Electrical and Information Technology, Lund University, 221 00 Lund, Sweden
| | - Johannes Svensson
- Division of Electromagnetics and Nanoelectronics, Department of Electrical and Information Technology, Lund University, 221 00 Lund, Sweden
| | - Adam Jönsson
- Division of Electromagnetics and Nanoelectronics, Department of Electrical and Information Technology, Lund University, 221 00 Lund, Sweden
| | - Lars-Erik Wernersson
- Division of Electromagnetics and Nanoelectronics, Department of Electrical and Information Technology, Lund University, 221 00 Lund, Sweden
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Mauthe S, Tiwari P, Scherrer M, Caimi D, Sousa M, Schmid H, Moselund KE, Vico Triviño N. Hybrid III-V Silicon Photonic Crystal Cavity Emitting at Telecom Wavelengths. NANO LETTERS 2020; 20:8768-8772. [PMID: 33216555 DOI: 10.1021/acs.nanolett.0c03634] [Citation(s) in RCA: 3] [Impact Index Per Article: 0.8] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/11/2023]
Abstract
Photonic crystal (PhC) cavities are promising candidates for Si photonics integrated circuits due to their ultrahigh quality (Q)-factors and small mode volumes. Here, we demonstrate a novel concept of a one-dimensional hybrid III-V/Si PhC cavity which exploits a combination of standard silicon-on-insulator technology and active III-V materials. Using template-assisted selective epitaxy, the central part of a Si PhC lattice is locally replaced with III-V gain material. The III-V material is placed to overlap with the maximum of the cavity mode field profile, while keeping the major part of the PhC in Si. The selective epitaxy process enables growth parallel to the substrate, and hence in-plane integration with Si, and in-situ in-plane homo- and heterojunctions. The fabricated hybrid III-V/Si PhCs show emission over the entire telecommunication band from 1.2 to 1.6 μm at room temperature validating the device concept and its potential towards fully integrated light sources on silicon.
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Affiliation(s)
- Svenja Mauthe
- IBM Research Europe, Säumerstrasse 4, 8803 Rüschlikon, Switzerland
| | - Preksha Tiwari
- IBM Research Europe, Säumerstrasse 4, 8803 Rüschlikon, Switzerland
| | - Markus Scherrer
- IBM Research Europe, Säumerstrasse 4, 8803 Rüschlikon, Switzerland
| | - Daniele Caimi
- IBM Research Europe, Säumerstrasse 4, 8803 Rüschlikon, Switzerland
| | - Marilyne Sousa
- IBM Research Europe, Säumerstrasse 4, 8803 Rüschlikon, Switzerland
| | - Heinz Schmid
- IBM Research Europe, Säumerstrasse 4, 8803 Rüschlikon, Switzerland
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8
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Gluschke JG, Seidl J, Tan HH, Jagadish C, Caroff P, Micolich AP. Impact of invasive metal probes on Hall measurements in semiconductor nanostructures. NANOSCALE 2020; 12:20317-20325. [PMID: 33006359 DOI: 10.1039/d0nr04402d] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/11/2023]
Abstract
Recent advances in bottom-up growth are giving rise to a range of new two-dimensional nanostructures. Hall effect measurements play an important role in their electrical characterization. However, size constraints can lead to device geometries that deviate significantly from the ideal of elongated Hall bars with currentless contacts. Many devices using these new materials have a low aspect ratio and feature metal Hall probes that overlap with the semiconductor channel. This can lead to a significant distortion of the current flow. We present experimental data from InAs 2D nanofin devices with different Hall probe geometries to study the influence of Hall probe length and width. We use finite-element simulations to further understand the implications of these aspects and expand their scope to contact resistance and sample aspect ratio. Our key finding is that invasive probes lead to significant underestimation of measured Hall voltage, typically of the order 40-80%. This in turn leads to a subsequent proportional overestimation of carrier concentration and an underestimation of mobility.
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Affiliation(s)
- Jan G Gluschke
- School of Physics, University of New South Wales, Sydney, NSW 2052, Australia.
| | - Jakob Seidl
- School of Physics, University of New South Wales, Sydney, NSW 2052, Australia.
| | - H Hoe Tan
- Department of Electronic Materials Engineering, Research School of Physics, The Australian National University, Canberra, ACT 2601, Australia
| | - Chennupati Jagadish
- Department of Electronic Materials Engineering, Research School of Physics, The Australian National University, Canberra, ACT 2601, Australia
| | - Philippe Caroff
- Department of Electronic Materials Engineering, Research School of Physics, The Australian National University, Canberra, ACT 2601, Australia and Microsoft Quantum Lab Delft, Delft University of Technology, 2600 GA, Delft, The Netherlands
| | - Adam P Micolich
- School of Physics, University of New South Wales, Sydney, NSW 2052, Australia.
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9
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High-speed III-V nanowire photodetector monolithically integrated on Si. Nat Commun 2020; 11:4565. [PMID: 32917898 PMCID: PMC7486389 DOI: 10.1038/s41467-020-18374-z] [Citation(s) in RCA: 38] [Impact Index Per Article: 9.5] [Reference Citation Analysis] [Abstract] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 11/18/2019] [Accepted: 08/07/2020] [Indexed: 11/12/2022] Open
Abstract
Direct epitaxial growth of III-Vs on silicon for optical emitters and detectors is an elusive goal. Nanowires enable the local integration of high-quality III-V material, but advanced devices are hampered by their high-aspect ratio vertical geometry. Here, we demonstrate the in-plane monolithic integration of an InGaAs nanostructure p-i-n photodetector on Si. Using free space coupling, photodetectors demonstrate a spectral response from 1200-1700 nm. The 60 nm thin devices, with footprints as low as ~0.06 μm2, provide an ultra-low capacitance which is key for high-speed operation. We demonstrate high-speed optical data reception with a nanostructure photodetector at 32 Gb s−1, enabled by a 3 dB bandwidth exceeding ~25 GHz. When operated as light emitting diode, the p-i-n devices emit around 1600 nm, paving the way for future fully integrated optical links. Direct epitaxial growth of III-V on Si for optical emitters and detectors remains a challenge. Here, the authors demonstrate in-plane monolithic integration of an InGaAs nanostructure p-i-n photodetector on Si capable of high-speed optical data reception at 32 Gbps enabled by a 3 dB bandwidth exceeding 25 GHz.
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10
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Jany BR, Janas A, Piskorz W, Szajna K, Kryshtal A, Cempura G, Indyka P, Kruk A, Czyrska-Filemonowicz A, Krok F. Towards the understanding of the gold interaction with AIII-BV semiconductors at the atomic level. NANOSCALE 2020; 12:9067-9081. [PMID: 32285065 DOI: 10.1039/c9nr10256f] [Citation(s) in RCA: 2] [Impact Index Per Article: 0.5] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/11/2023]
Abstract
AIII-BV semiconductors have been considered to be a promising material for decades in overcoming the limitations of silicon semiconductor devices. One of the important aspects within the AIII-BV semiconductor technology is gold-semiconductor interactions on the nanoscale. We report on the investigations into the basic chemical interactions of Au atoms with AIII-BV semiconductor crystals by the investigation of the nanostructure formation in the process of thermally-induced Au self-assembly on various AIII-BV surfaces by means of atomically resolved High Angle Annular Dark Field (HAADF) Scanning Transmission Electron Microscopy (STEM) measurements. We have found that the formation of nanostructures is a consequence of the surface diffusion and nucleation of adatoms produced by Au induced chemical reactions on AIII-BV semiconductor surfaces. Only for InSb crystals we have found that there is efficient diffusion of Au atoms into the bulk, which we experimentally studied by Machine Learning HAADF STEM image quantification and theoretically by Density Functional Theory (DFT) calculations with the inclusion of finite temperature effects. Furthermore, the effective number of Au atoms needed to release one AIII metal atom has been estimated. The experimental finding reveals a difference in the Au interactions with the In- and Ga-based groups of AIII-BV semiconductors. Our comprehensive and systematic studies uncover the details of the Au interactions with the AIII-BV surface at the atomic level with chemical sensitivity and shed new light on the fundamental Au/AIII-BV interactions at the atomic scale.
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Affiliation(s)
- B R Jany
- The Marian Smoluchowski Institute of Physics, Jagiellonian University, Lojasiewicza 11, 30-348 Krakow, Poland.
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11
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Nano-Ridge Engineering of GaSb for the Integration of InAs/GaSb Heterostructures on 300 mm (001) Si. CRYSTALS 2020. [DOI: 10.3390/cryst10040330] [Citation(s) in RCA: 19] [Impact Index Per Article: 4.8] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 11/16/2022]
Abstract
Nano-ridge engineering (NRE) is a novel heteroepitaxial approach for the monolithic integration of lattice-mismatched III-V devices on Si substrates. It has been successfully applied to GaAs for the realization of nano-ridge (NR) laser diodes and heterojunction bipolar transistors on 300 mm Si wafers. In this report we extend NRE to GaSb for the integration of narrow bandgap heterostructures on Si. GaSb is deposited by selective area growth in narrow oxide trenches fabricated on 300 mm Si substrates to reduce the defect density by aspect ratio trapping. The GaSb growth is continued and the NR shape on top of the oxide pattern is manipulated via NRE to achieve a broad (001) NR surface. The impact of different seed layers (GaAs and InAs) on the threading dislocation and planar defect densities in the GaSb NRs is investigated as a function of trench width by using transmission electron microscopy (TEM) as well as electron channeling contrast imaging (ECCI), which provides significantly better defect statistics in comparison to TEM only. An InAs/GaSb multi-layer heterostructure is added on top of an optimized NR structure. The high crystal quality and low defect density emphasize the potential of this monolithic integration approach for infrared optoelectronic devices on 300 mm Si substrates.
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12
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Hu R, Ma H, Yin H, Xu J, Chen K, Yu L. Facile 3D integration of Si nanowires on Bosch-etched sidewalls for stacked channel transistors. NANOSCALE 2020; 12:2787-2792. [PMID: 31960875 DOI: 10.1039/c9nr09000b] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/10/2023]
Abstract
Three-dimensional (3D) integration is a promising strategy to integrate more functions into a given footprint. In this work, we report on a convenient new strategy to grow and integrate high density Si nanowire (SiNW) arrays on the parallel sidewall grooves formed by Bosch etching, via a low temperature (<350 °C) in-plane solid-liquid-solid (IPSLS) mechanism. It is observed that both the pitch and the depth of the grooves can be reliably controlled, by tuning the Bosch etching parameters, to adjust the density of SiNWs, and the sidewall growth of SiNWs is rather stable even along the turnings. This approach has demonstrated a facile batch-manufacturing of stacked SiNWs, where the SiNWs exhibit a mean diameter of 40 nm and a spacing of 100 nm, without the use of any high resolution lithography. Prototype stacked channel transistors are also fabricated, with an impressive on/off current of >107 and a hole mobility of 57 cm2 V-1 s-1, in a unique vertical side-gate configuration. These results highlight the unique potential and benefit of combining conventional Bosch processing with high precision 3D guided growth of SiNWs for constructing more complex and functional stacked channel electronics.
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Affiliation(s)
- Ruijin Hu
- National Laboratory of Solid State Microstructures/School of Electronics Science and Engineering/Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing, 210093, P. R. China.
| | - Haiguang Ma
- National Laboratory of Solid State Microstructures/School of Electronics Science and Engineering/Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing, 210093, P. R. China.
| | - Han Yin
- National Laboratory of Solid State Microstructures/School of Electronics Science and Engineering/Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing, 210093, P. R. China.
| | - Jun Xu
- National Laboratory of Solid State Microstructures/School of Electronics Science and Engineering/Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing, 210093, P. R. China.
| | - Kunji Chen
- National Laboratory of Solid State Microstructures/School of Electronics Science and Engineering/Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing, 210093, P. R. China.
| | - Linwei Yu
- National Laboratory of Solid State Microstructures/School of Electronics Science and Engineering/Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing, 210093, P. R. China.
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13
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Sun J, Peng M, Zhang Y, Zhang L, Peng R, Miao C, Liu D, Han M, Feng R, Ma Y, Dai Y, He L, Shan C, Pan A, Hu W, Yang ZX. Ultrahigh Hole Mobility of Sn-Catalyzed GaSb Nanowires for High Speed Infrared Photodetectors. NANO LETTERS 2019; 19:5920-5929. [PMID: 31374165 DOI: 10.1021/acs.nanolett.9b01503] [Citation(s) in RCA: 24] [Impact Index Per Article: 4.8] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 05/28/2023]
Abstract
Owing to the relatively low hole mobility, the development of GaSb nanowire (NW) electronic and photoelectronic devices has stagnated in the past decade. During a typical catalyst-assisted chemical vapor deposition (CVD) process, the adopted metallic catalyst can be incorporated into the NW body to act as a slight dopant, thus regulating the electrical properties of the NW. In this work, we demonstrate the use of Sn as a catalyst and dopant for GaSb NWs in the surfactant-assisted CVD growth process. The Sn-catalyzed zinc-blende GaSb NWs are thin, long, and straight with good crystallinity, resulting in a record peak hole mobility of 1028 cm2 V-1 s-1. This high mobility is attributed to the slight doping of Sn atoms from the catalyst tip into the NW body, which is verified by the red-shifted photoluminescence peak of Sn-catalyzed GaSb NWs (0.69 eV) compared with that of Au-catalyzed NWs (0.74 eV). Furthermore, the parallel array NWs also show a high peak hole mobility of 170 cm2 V-1 s-1, a high responsivity of 61 A W-1, and fast rise and decay times of 195.1 and 380.4 μs, respectively, under the illumination of 1550 nm infrared light. All of the results demonstrate that the as-prepared Sn-catalyzed GaSb NWs are promising for application in next-generation electronics and optoelectronics.
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Affiliation(s)
- Jiamin Sun
- School of Microelectronics , Shandong University , Jinan 250100 , P. R. China
- Shenzhen Research Institute of Shandong University , Shenzhen 518057 , P. R. China
| | - Meng Peng
- State Key Laboratory of Infrared Physics , Shanghai Institute of Technical Physics, Chinese Academy of Sciences , Shanghai 200083 , P. R. China
- Wuhan National Laboratory for Optoelectronics , Huazhong University of Science and Technology , Wuhan 430074 , China
| | - Yushuang Zhang
- Key Laboratory for Micro-Nano Physics and Technology of Hunan Province, College of Materials Science and Engineering , Hunan University , Changsha 410082 , P. R. China
| | - Lei Zhang
- SEU-FEI Nano-Pico Center, Key Lab of MEMS of Ministry of Education, Collaborative Innovation Center for Micro/Nano Fabrication, Device and System , Southeast University , Nanjing 210096 , P. R. China
| | - Rui Peng
- School of Physics , Shandong University , Jinan 250100 , P. R. China
| | - Chengcheng Miao
- School of Microelectronics , Shandong University , Jinan 250100 , P. R. China
| | - Dong Liu
- School of Microelectronics , Shandong University , Jinan 250100 , P. R. China
| | - Mingming Han
- School of Microelectronics , Shandong University , Jinan 250100 , P. R. China
- Shenzhen Research Institute of Shandong University , Shenzhen 518057 , P. R. China
| | - Runfa Feng
- School of Physics , Shandong University , Jinan 250100 , P. R. China
| | - Yandong Ma
- School of Physics , Shandong University , Jinan 250100 , P. R. China
| | - Ying Dai
- School of Physics , Shandong University , Jinan 250100 , P. R. China
| | - Longbing He
- SEU-FEI Nano-Pico Center, Key Lab of MEMS of Ministry of Education, Collaborative Innovation Center for Micro/Nano Fabrication, Device and System , Southeast University , Nanjing 210096 , P. R. China
| | - Chongxin Shan
- Henan Key Laboratory of Diamond Optoelectronic Materials and Devices, School of Physics and Engineering , Zhengzhou University , Zhengzhou 450001 , China
| | - Anlian Pan
- Key Laboratory for Micro-Nano Physics and Technology of Hunan Province, College of Materials Science and Engineering , Hunan University , Changsha 410082 , P. R. China
| | - Weida Hu
- State Key Laboratory of Infrared Physics , Shanghai Institute of Technical Physics, Chinese Academy of Sciences , Shanghai 200083 , P. R. China
| | - Zai-Xing Yang
- School of Microelectronics , Shandong University , Jinan 250100 , P. R. China
- Shenzhen Research Institute of Shandong University , Shenzhen 518057 , P. R. China
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14
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Yip S, Shen L, Ho JC. Recent advances in III-Sb nanowires: from synthesis to applications. NANOTECHNOLOGY 2019; 30:202003. [PMID: 30625448 DOI: 10.1088/1361-6528/aafcce] [Citation(s) in RCA: 7] [Impact Index Per Article: 1.4] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 05/28/2023]
Abstract
The excellent properties of III-V semiconductors make them intriguing candidates for next-generation electronics and optoelectronics. Their nanowire (NW) counterparts further provide interesting geometry and a quantum confinement effect which benefits various applications. Among the many members of all the III-V semiconductors, III-antimonide NWs have attracted significant research interest due to their narrow, direct bandgap and high carrier mobility. However, due to the difficulty of NW fabrication, the development of III-antimonide NWs and their corresponding applications are always a step behind the other III-V semiconductors. Until recent years, because of advances in understanding and fabrication techniques, electronic and optoelectronic devices based on III-antimonide NWs with novel performance have been fabricated. In this review, we will focus on the development of the synthesis of III-antimonide NWs using different techniques and strategies for fine-tuning the crystal structure and composition as well as fabricating their corresponding heterostructures. With such development, the recent progress in the applications of III-antimonide NWs in electronics and optoelectronics is also surveyed. All these discussions provide valuable guidelines for the design of III-antimonide NWs for next-generation device utilization.
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Affiliation(s)
- SenPo Yip
- Department of Materials Science and Engineering, City University of Hong Kong, Hong Kong Special Administrative Region of China, People's Republic of China. Shenzhen Research Institute, City University of Hong Kong, Shenzhen 518057, People's Republic of China
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15
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Convertino C, Zota CB, Schmid H, Ionescu AM, Moselund KE. III-V heterostructure tunnel field-effect transistor. JOURNAL OF PHYSICS. CONDENSED MATTER : AN INSTITUTE OF PHYSICS JOURNAL 2018; 30:264005. [PMID: 29771239 DOI: 10.1088/1361-648x/aac5b4] [Citation(s) in RCA: 4] [Impact Index Per Article: 0.7] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 05/07/2023]
Abstract
The tunnel field-effect transistor (TFET) is regarded as one of the most promising solid-state switches to overcome the power dissipation challenge in ultra-low power integrated circuits. TFETs take advantage of quantum mechanical tunneling hence exploit a different current control mechanism compared to standard MOSFETs. In this review, we describe state-of-the-art development of TFET both in terms of performances and of materials integration and we identify the main remaining technological challenges such as heterojunction defects and oxide/channel interface traps causing trap-assisted-tunneling (TAT). Mesa-structures, planar as well as vertical geometries are examined. Conductance slope analysis on InAs/GaSb nanowire tunnel diodes are reported, these two-terminal measurements can be relevant to investigate the tunneling behavior. A special focus is dedicated to III-V heterostructure TFET, as different groups have recently shown encouraging results achieving the predicted sub-thermionic low-voltage operation.
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