Low operating bias and matched input-output characteristics in graphene logic inverters

The Roadmap of 2D Materials and Devices Toward Chips

Due to the constraints imposed by physical effects and performance degradation, silicon-based chip technology is facing certain limitations in sustaining the advancement of Moore's law. Two-dimensional (2D) materials have emerged as highly promising candidates for the post-Moore era, offering significant potential in domains such as integrated circuits and next-generation computing. Here, in this review, the progress of 2D semiconductors in process engineering and various electronic applications are summarized. A careful introduction of material synthesis, transistor engineering focused on device configuration, dielectric engineering, contact engineering, and material integration are given first. Then 2D transistors for certain electronic applications including digital and analog circuits, heterogeneous integration chips, and sensing circuits are discussed. Moreover, several promising applications (artificial intelligence chips and quantum chips) based on specific mechanism devices are introduced. Finally, the challenges for 2D materials encountered in achieving circuit-level or system-level applications are analyzed, and potential development pathways or roadmaps are further speculated and outlooked.

Unveiling the impact of the bias-dependent charge neutrality point on graphene based multi-transistor applications

The Dirac voltage of a graphene field-effect transistor (GFET) stands for the gate bias that sets the charge neutrality condition in the channel, thus resulting in a minimum conductivity. Controlling its dependence on the terminal biases is crucial for the design and optimization of radio-frequency applications based on multiple GFETs. However, the previous analysis of such dependence carried out for single devices is uncomplete and if not properly understood could result in circuit designs with poor performance. The control of the Dirac point shift (DPS) is particularly important for the deployment of graphene-based differential circuit topologies where keeping a strict symmetry between the electrically balanced branches is essential for exploiting the advantages of such topologies. This note sheds light on the impact of terminal biases on the DPS in a real device and sets a rigorous methodology to control it so to eventually optimize and exploit the performance of radio-frequency applications based on GFETs.

Ambipolar 2D Semiconductors and Emerging Device Applications

With the rise of 2D materials, new physics and new processing techniques have emerged, triggering possibilities for the innovation of electronic and optoelectronic devices. Among them, ambipolar 2D semiconductors are of excellent gate-controlled capability and distinctive physical characteristic that the major charge carriers can be dynamically, reversibly and rapidly tuned between holes and electrons by electrostatic field. Based on such properties, novel devices, like ambipolar field-effect transistors, light-emitting transistors, electrostatic-field-charging PN diodes, are developed and show great advantages in logic and reconfigurable circuits, integrated optoelectronic circuits, and artificial neural network image sensors, enriching the functions of conventional devices and bringing breakthroughs to build new architectures. This review first focuses on the basic knowledge including fundamental principle of ambipolar semiconductors, basic material preparation techniques, and how to obtain the ambipolar behavior through electrical contact engineering. Then, the current ambipolar 2D semiconductors and their preparation approaches and main properties are summarized. Finally, the emerging new device structures are overviewed in detail, along with their novel electronic and optoelectronic applications. It is expected to shed light on the future development of ambipolar 2D semiconductors, exploring more new devices with novel functions and promoting the applications of 2D materials.

Designing Dual-Function Nanostructures for Water Purification in Sunlight

The current study aims at combining two building blocks together into well-designed nanostructures to act as dual-function materials; active photocatalysts in sunlight and effective adsorbents for increasing the efficiency of water purification. By these nanostructures, we could avoid the drawbacks of the existing technologies for water purification and remove the industrial pollutants by a dual process; adsorption and photocatalytic degradation. In this trend, Zn-Al layered double hydroxides (LDHs) are combined with graphene oxide to produce a series of nanolayered structures. These nanolayered structures are effective for converting Zn-Al LDHs to be photo-active in sunlight through decreasing its band gap energy from 5.5 eV to 2.5 eV. In addition, these nanolayered structures caused complete decolorization and mineralization of green dyes in sunlight through accelerating the reaction rate of the photocatalytic degradation of dyes seven times higher than that of the pure Zn-Al LDHs. In the same time, they improved the adsorption process of green dyes through creating new micro- and meso-porous structures and high surface area for Zn-Al LDHs. Finally, the well-designed nanostructures between Zn-Al LDHs and graphene oxide led to converting non-photoactive materials to be active in the visible light in addition to a complete and fast removal for organic pollutants.

Low-Power Complementary Logic Circuit Using Polymer-Electrolyte-Gated Graphene Switching Devices

The modulation of the electrical properties of graphene and its device configurations for low-power consumption are important in developing graphene-based logic electronics. Here, we demonstrate the change in the charge transport in graphene from ambipolar to unipolar using surface charge transfer doping of the polymer electrolyte. Unipolar graphene field-effect transistors (GFETs) were obtained by the surface treatment of poly(acrylic acid) (PAA) for p-type and poly(ethyleneimine) (PEI) for n-type as polymer-electrolyte gates. In addition, lithium perchlorate (LiClO₄) in a polymer matrix can be used for the low-gate voltage operation of GFETs (less than ±3 V) because of its high gating efficiency. Using polymer-electrolyte-gated GFETs, complementary graphene inverters were fabricated with a voltage swing of 57% and maximum voltage gain (V_gain) of 1.1 at a low supply voltage (V_DD = 1 V). This is expected to facilitate the development of graphene-based logic devices with low-cost, low-power, and flexible electronics.

Vertically Stacked CVD-Grown 2D Heterostructure for Wafer-Scale Electronics

This paper demonstrates, for the first time, wafer-scale graphene/MoS₂ heterostructures prepared by chemical vapor deposition (CVD) and their application in vertical transistors and logic gates. A CVD-grown bulk MoS₂ layer is utilized as the vertical channel, whereas CVD-grown monolayer graphene is used as the tunable work-function electrode. The short vertical channel of the transistor is formed by sandwiching bulk MoS₂ between the bottom indium tin oxide (ITO, drain electrode) and the top graphene (source electrode). The electron injection barriers at the graphene-MoS₂ junction and ITO-MoS₂ junction are modulated effectively through variation of the Schottky barrier height and its effective barrier width, respectively, because of the work-function tunability of the graphene electrode. The resulting vertical transistor with the CVD-grown MoS₂/graphene heterostructure exhibits a current density exceeding 7 A/cm², a subthreshold swing of 410 mV/dec, and an on-off current ratio exceeding 10³. The large-area synthesis, transfer, and patterning processes of both semiconducting MoS₂ and metallic graphene facilitate construction of a wafer-scale array of transistors and logic gates such as NOT, NAND, and NOR.

Mechanosensation-Active Matrix Based on Direct-Contact Tribotronic Planar Graphene Transistor Array

Mechanosensitive electronics aims at replicating the multifunctions of human skin to realize quantitative conversion of external stimuli into electronic signals and provide corresponding feedback instructions. Here, we report a mechanosensation-active matrix based on a direct-contact tribotronic planar graphene transistor array. Ion gel is utilized as both the dielectric in the graphene transistor and the friction layer for triboelectric potential coupling to achieve highly efficient gating and sensation properties. Different contact distances between the ion gel and other friction materials produce different triboelectric potentials, which are directly coupled to the graphene channel and lead to different output signals through modulating the Fermi level of graphene. Based on this mechanism, the tribotronic graphene transistor is capable of sensing approaching distances, recognizing the category of different materials, and even distinguishing voices. It possesses excellent sensing properties, including high sensitivity (0.16 mm^-1), fast response time (∼15 ms), and excellent durability (over 1000 cycles). Furthermore, the fabricated mechanosensation-active matrix is demonstrated to sense spatial contact distances and visualize a 2D color mapping of the target object. The tribotronic active matrix with ion gel as dielectric/friction layer provides a route for efficient and low-power-consuming mechanosensation in a noninvasive fashion. It is of great significance in multifunction sensory systems, wearable human-machine interactive interfaces, artificial electronic skin, and future telemedicine for patient surveillance.

Printed Electronics Based on Inorganic Semiconductors: From Processes and Materials to Devices

Following the ever-expanding technological demands, printed electronics has shown palpable potential to create new and commercially viable technologies that will benefit from its unique characteristics, such as, large-area and wide range of substrate compatibility, conformability and low-cost. Through the last few decades, printed/solution-processed field-effect transistors (FETs) and circuits have witnessed immense research efforts, technological growth and increased commercial interests. Although printing of functional inks comprising organic semiconductors has already been initiated in early 1990s, gradually the attention, at least partially, has been shifted to various forms of inorganic semiconductors, starting from metal chalcogenides, oxides, carbon nanotubes and very recently to graphene and other 2D semiconductors. In this review, the entire domain of printable inorganic semiconductors is considered. In fact, thanks to the continuous development of materials/functional inks and novel design/printing strategies, the inorganic printed semiconductor-based circuits today have reached an operation frequency up to several hundreds of kilohertz with only a few nanosecond time delays at the individual FET/inverter levels; in this regard, often circuits based on hybrid material systems have been found to be advantageous. At the end, a comparison of relative successes of various printable inorganic semiconductor materials, the remaining challenges and the available future opportunities are summarized.

Chemically induced Fermi level pinning effects of high-k dielectrics on graphene

High-k materials such as Al₂O₃ and HfO₂ are widely used as gate dielectrics in graphene devices. However, the effective work function values of metal gate in graphene FET are significantly deviated from their vacuum work function, which is similar to the Fermi level pinning effect observed in silicon MOSFETs with high-k dielectric. The degree of deviation represented by a pinning factor was much worse with HfO₂ (pinning factor (S) = 0.19) than with Al₂O₃ (S = 0.69). We propose that the significant pinning-like behaviors induced by HfO₂ are correlated with the oxygen exchange reactions occurred at the interface of graphene and HfO₂.

Fully inkjet-printed two-dimensional material field-effect heterojunctions for wearable and textile electronics

Fully printed wearable electronics based on two-dimensional (2D) material heterojunction structures also known as heterostructures, such as field-effect transistors, require robust and reproducible printed multi-layer stacks consisting of active channel, dielectric and conductive contact layers. Solution processing of graphite and other layered materials provides low-cost inks enabling printed electronic devices, for example by inkjet printing. However, the limited quality of the 2D-material inks, the complexity of the layered arrangement, and the lack of a dielectric 2D-material ink able to operate at room temperature, under strain and after several washing cycles has impeded the fabrication of electronic devices on textile with fully printed 2D heterostructures. Here we demonstrate fully inkjet-printed 2D-material active heterostructures with graphene and hexagonal-boron nitride (h-BN) inks, and use them to fabricate all inkjet-printed flexible and washable field-effect transistors on textile, reaching a field-effect mobility of ~91 cm2 V-1 s-1, at low voltage (<5 V). This enables fully inkjet-printed electronic circuits, such as reprogrammable volatile memory cells, complementary inverters and OR logic gates.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Graphene-Based Flexible and Stretchable Electronics

Graphene provides outstanding properties that can be integrated into various flexible and stretchable electronic devices in a conventional, scalable fashion. The mechanical, electrical, and optical properties of graphene make it an attractive candidate for applications in electronics, energy-harvesting devices, sensors, and other systems. Recent research progress on graphene-based flexible and stretchable electronics is reviewed here. The production and fabrication methods used for target device applications are first briefly discussed. Then, the various types of flexible and stretchable electronic devices that are enabled by graphene are discussed, including logic devices, energy-harvesting devices, sensors, and bioinspired devices. The results represent important steps in the development of graphene-based electronics that could find applications in the area of flexible and stretchable electronics.

Highly Flexible and High-Performance Complementary Inverters of Large-Area Transition Metal Dichalcogenide Monolayers

Complementary inverters constructed from large-area monolayers of WSe2 and MoS2 achieve excellent logic swings and yield an extremely high gain, large total noise margin, low power consumption, and good switching speed. Moreover, the WSe2 complementary-like inverters built on plastic substrates exhibit high mechanical stability. The results provide a path toward large-area flexible electronics.

Graphene Ambipolar Nanoelectronics for High Noise Rejection Amplification

In a modern wireless communication system, signal amplification is critical for overcoming losses during multiple data transformations/processes and long-distance transmission. Common mode and differential mode are two fundamental amplification mechanisms, and they utilize totally different circuit configurations. In this paper, we report a new type of dual-gate graphene ambipolar device with capability of operating under both common and differential modes to realize signal amplification. The signal goes through two stages of modulation where the phase of signal can be individually modulated to be either in-phase or out-of-phase at two stages by exploiting the ambipolarity of graphene. As a result, both common and differential mode amplifications can be achieved within one single device, which is not possible in the conventional circuit configuration. In addition, a common-mode rejection ratio as high as 80 dB can be achieved, making it possible for low noise circuit application. These results open up new directions of graphene-based ambipolar electronics that greatly simplify the RF circuit complexity and the design of multifunction device operation.

Charge transport and mobility engineering in two-dimensional transition metal chalcogenide semiconductors

This review presents recent progress on charge transport properties, carrier scattering mechanisms, and carrier mobility engineering of two-dimensional transition metal chalcogenides.

Integrated digital inverters based on two-dimensional anisotropic ReS2 field-effect transistors

Semiconducting two-dimensional transition metal dichalcogenides are emerging as top candidates for post-silicon electronics. While most of them exhibit isotropic behaviour, lowering the lattice symmetry could induce anisotropic properties, which are both scientifically interesting and potentially useful. Here we present atomically thin rhenium disulfide (ReS₂) flakes with unique distorted 1T structure, which exhibit in-plane anisotropic properties. We fabricated monolayer and few-layer ReS₂ field-effect transistors, which exhibit competitive performance with large current on/off ratios (∼10⁷) and low subthreshold swings (100 mV per decade). The observed anisotropic ratio along two principle axes reaches 3.1, which is the highest among all known two-dimensional semiconducting materials. Furthermore, we successfully demonstrated an integrated digital inverter with good performance by utilizing two ReS₂ anisotropic field-effect transistors, suggesting the promising implementation of large-scale two-dimensional logic circuits. Our results underscore the unique properties of two-dimensional semiconducting materials with low crystal symmetry for future electronic applications.

Many two-dimensional materials exhibit isotropic properties, but anisotropy can extend the functionality of future devices. Here, the authors fabricate field-effect transistors from single and few-layer rhenium disulfide and observe an anisotropic ratio of three to one along the two principle axes

Scaling of graphene integrated circuits

The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

Vertically architectured stack of multiple graphene field-effect transistors for flexible electronics

Vertically architectured stack of multiple graphene field-effect transistors (GFETs) on a flexible substrate show great mechanical flexibility and robustness. The four GFETs are integrated in the vertical direction, and dually gated GFETs with graphene channel, PMMA dielectrics, and graphene gate electrodes are realized.

Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems

We present the science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems, targeting an evolution in technology, that might lead to impacts and benefits reaching into most areas of society. This roadmap was developed within the framework of the European Graphene Flagship and outlines the main targets and research areas as best understood at the start of this ambitious project. We provide an overview of the key aspects of graphene and related materials (GRMs), ranging from fundamental research challenges to a variety of applications in a large number of sectors, highlighting the steps necessary to take GRMs from a state of raw potential to a point where they might revolutionize multiple industries. We also define an extensive list of acronyms in an effort to standardize the nomenclature in this emerging field.

Flexible black phosphorus ambipolar transistors, circuits and AM demodulator

High-mobility two-dimensional (2D) semiconductors are desirable for high-performance mechanically flexible nanoelectronics. In this work, we report the first flexible black phosphorus (BP) field-effect transistors (FETs) with electron and hole mobilities superior to what has been previously achieved with other more studied flexible layered semiconducting transistors such as MoS2 and WSe2. Encapsulated bottom-gated BP ambipolar FETs on flexible polyimide afforded maximum carrier mobility of about 310 cm(2)/V·s with field-effect current modulation exceeding 3 orders of magnitude. The device ambipolar functionality and high-mobility were employed to realize essential circuits of electronic systems for flexible technology including ambipolar digital inverter, frequency doubler, and analog amplifiers featuring voltage gain higher than other reported layered semiconductor flexible amplifiers. In addition, we demonstrate the first flexible BP amplitude-modulated (AM) demodulator, an active stage useful for radio receivers, based on a single ambipolar BP transistor, which results in audible signals when connected to a loudspeaker or earphone. Moreover, the BP transistors feature mechanical robustness up to 2% uniaxial tensile strain and up to 5000 bending cycles.

Highly air stable passivation of graphene based field effect devices

The sensitivity of graphene based devices to surface adsorbates and charge traps at the graphene/dielectric interface requires proper device passivation in order to operate them reproducibly under ambient conditions. Here we report on the use of atomic layer deposited aluminum oxide as passivation layer on graphene field effect devices (GFETs). We show that successful passivation produce hysteresis free DC characteristics, low doping level GFETs stable over weeks though operated and stored in ambient atmosphere. This is achieved by selecting proper seed layer prior to deposition of encapsulation layer. The passivated devices are also demonstrated to be robust towards the exposure to chemicals and heat treatments, typically used during device fabrication. Additionally, the passivation of high stability and reproducible characteristics is also shown for functional devices like integrated graphene based inverters.

Nanoelectronic circuits based on two-dimensional atomic layer crystals

Since the discovery of graphene and related forms of two-dimensional (2D) atomic layer crystals, numerous studies have reported on the fundamental material aspects, such as the synthesis, the physical properties, and the electrical properties on the transistor level. With the advancement in large-area synthesis methods, system level integration to exploit the unique applications of these materials is close at hand. The main purpose of this review is to focus on the current progress and the prospect of circuits and systems based on 2D material that go beyond the single-transistor level studies. Both analog and digital circuits based on graphene and related 2D atomic layer crystals will be discussed.

Superlattice assembly of graphene oxide (GO) and titania nanosheets: fabrication, in situ photocatalytic reduction of GO and highly improved carrier transport

Two different kinds of two-dimensional (2D) materials, graphene oxide (GO) and titanium oxide nanosheets (Ti₀.₈₇O2(0.52-)), were self-assembled layer-by-layer using a polycation as a linker into a superlattice film. Successful construction of an alternate molecular assembly was confirmed by atomic force microscopy and UV-visible absorption spectroscopy as well as X-ray diffraction analysis. Exposure of the resulting film to UV light effectively promoted photocatalytic reduction of GO as well as decomposition of the polycation, which are due to their intimate molecular-level contact. The reduction completed within 3 hours, bringing about a decrease of the sheet resistance by ∼10(6). This process provides a clean and mild route to reduced graphene oxide (rGO), showing advantages over other chemical and thermal reduction processes. A field-effect-transistor device was fabricated using the resulting superlattice assembly of rGO/Ti₀.₈₇O₂(0.52-) as a channel material. The rGO in the film was found to work as a unipolar n-type conductor, which is in contrast to ambipolar or unipolar p-type behavior mostly reported for rGO films. This unique property may be associated with the electron doping effect from Ti₀.₈₇O₂(0.52-) nanosheets. A significant improvement in the conductance and electron carrier mobility by more than one order of magnitude was revealed, which may be accounted for by the heteroassembly with Ti₀.₈₇(0.52-) nanosheets with a high dielectric constant as well as the better 2D structure of rGO produced via the soft photocatalytic reduction.

Graphene field-effect transistor and its application for electronic sensing

Graphene, because of its excellent mechanical, electrical, chemical, physical properties, sparked great interest to develop and extend its applications. Particularly, graphene based field-effect transistors (GFETs) present exciting and bright prospects for sensing applications due to their greatly higher sensitivity and stronger selectivity. This Review highlights a selection of important topics pertinent to GFETs and their application in electronic sensors. This article begins with a description of the fabrications and characterizations of GFETs, and then introduces the new developments in physical, chemical, and biological electronic detection using GFETs. Finally, several perspective and current challenges of GFETs development are presented, and some proposals are suggested for further development and exploration.

Barrier inhomogeneities at vertically stacked graphene-based heterostructures

The integration of graphene and other atomically flat, two-dimensional materials has attracted much interest and been materialized very recently. An in-depth understanding of transport mechanisms in such heterostructures is essential. In this study, vertically stacked graphene-based heterostructure transistors were manufactured to elucidate the mechanism of electron injection at the interface. The temperature dependence of the electrical characteristics was investigated from 300 to 90 K. In a careful analysis of current-voltage characteristics, an unusual decrease in the effective Schottky barrier height and increase in the ideality factor were observed with decreasing temperature. A model of thermionic emission with a Gaussian distribution of barriers was able to precisely interpret the conduction mechanism. Furthermore, mapping of the effective Schottky barrier height is unmasked as a function of temperature and gate voltage. The results offer significant insight for the development of future layer-integration technology based on graphene-based heterostructures.

Photo-patternable ion gel-gated graphene transistors and inverters on plastic

We demonstrate photo-patternable ion gel-gated graphene transistors and inverters on plastic substrates. The photo-patternable ion gel can be used as a negative photoresist for the patterning of underlying graphene as well as gate dielectrics. As a result, an extra graphene-patterning step is not required, which simplifies the device fabrication and avoids a side effect arising from the photoresist residue. The high capacitance of ion gel gate dielectrics yielded a low voltage operation (~2 V) of the graphene transistor and inverter. The graphene transistors on plastic showed an on/off-current ratio of ~11.5, along with hole and electron mobilities of 852 ± 124 and 452 ± 98 cm(2) V(-1) s(-1), respectively. In addition, the flexible graphene inverter was successfully fabricated on plastic through the potential superposition effect from the drain bias. These devices show excellent mechanical flexibility and fatigue stability.

Suppression of thermally activated carrier transport in atomically thin MoS2 on crystalline hexagonal boron nitride substrates

We present the temperature-dependent carrier mobility of atomically thin MoS2 field-effect transistors on crystalline hexagonal boron nitride (h-BN) and SiO2 substrates. Our results reveal distinct weak temperature dependence of the MoS2 devices on h-BN substrates. The room temperature mobility enhancement and reduced interface trap density of the single and bilayer MoS2 devices on h-BN substrates further indicate that reducing substrate traps is crucial for enhancing the mobility in atomically thin MoS2 devices.

Highly tunable local gate controlled complementary graphene device performing as inverter and voltage controlled resistor

Using single-layer CVD graphene, a complementary field effect transistor (FET) device is fabricated on the top of separated back-gates. The local back-gate control of the transistors, which operate with low bias at room temperature, enables highly tunable device characteristics due to separate control over electrostatic doping of the channels. Local back-gating allows control of the doping level independently of the supply voltage, which enables device operation with very low VDD. Controllable characteristics also allow the compensation of variation in the unintentional doping typically observed in CVD graphene. Moreover, both p-n and n-p configurations of FETs can be achieved by electrostatic doping using the local back-gate. Therefore, the device operation can also be switched from inverter to voltage controlled resistor, opening new possibilities in using graphene in logic circuitry.

Gigahertz integrated graphene ring oscillators

Ring oscillators (ROs) are the most important class of circuits used to evaluate the performance limits of any digital technology. However, ROs based on low-dimensional nanomaterials (e.g., 1-D nanotubes, nanowires, 2-D MoS2) have so far exhibited limited performance due to low current drive or large parasitics. Here we demonstrate integrated ROs fabricated from wafer-scale graphene grown by chemical vapor deposition. The highest oscillation frequency was 1.28 GHz, while the largest output voltage swing was 0.57 V. Both values remain limited by parasitic capacitances in the circuit rather than intrinsic properties of the graphene transistor components, suggesting further improvements are possible. The fabricated ROs are the fastest realized in any low-dimensional nanomaterial to date and also the least sensitive to fluctuations in the supply voltage. They represent the first integrated graphene oscillators of any kind and can also be used in a wide range of applications in analog electronics. As a demonstration, we also realized the first stand-alone graphene mixers that do not require external oscillators for frequency conversion. The first gigahertz multitransistor graphene integrated circuits demonstrated here pave the way for application of graphene in high-speed digital and analog circuits in which high operating speed could be traded off against power consumption.

Carrier sheet density constrained anomalous current saturation of graphene field effect transistors: kinks and negative differential resistances

There has recently been a great deal of interest and excitement in applying graphene field effect transistors (GFETs) in digital and radio frequency (RF) circuits and systems. Peculiar output characteristics such as kinks and negative differential resistance (NDR) in a strong field are the unique transport properties of GFETs. Here we demonstrate that these unusual features are attributed to a carrier sheet density constrained transport framework. Simulation results based on a simple analytic model which includes the linear DOS structure are in very good agreement with experimental data. The kernel mechanism of NDR is ascribed to the fact that the total current increase of a channel with a high average carrier density is constrained by its minimum sheet density. Utilizing in situ Kelvin probe force microscopy (KPFM), the principle which naturally distinguishes NDR from kinks is further verified by studying the spatially resolved surface potential distribution along the channel. The influence and potential application of GFETs' unique output characteristics in the digital and RF fields are also proposed.

Coplanar-gate transparent graphene transistors and inverters on plastic

Transparent flexible graphene transistors and inverters in a coplanar-gate configuration were presented for the first time using only two materials: graphene and an ion gel gate dielectric. The novel device configuration simplifies device fabrication such that only two printing steps were required to fabricate transistors and inverters. The devices exhibited excellent device performances including low-voltage operation with a high transistor-on-current and mobility, excellent mechanical flexibility, environmental stability, and a reasonable inverting behavior upon connecting the two transistors.

Cascading wafer-scale integrated graphene complementary inverters under ambient conditions

The fundamental building blocks of digital electronics are logic gates which must be capable of cascading such that more complex logic functions can be realized. Here we demonstrate integrated graphene complementary inverters which operate with the same input and output voltage logic levels, thus allowing cascading. We obtain signal matching under ambient conditions with inverters fabricated from wafer-scale graphene grown by chemical vapor deposition (CVD). Monolayer graphene was incorporated in self-aligned field-effect transistors in which the top gate overlaps with the source and drain contacts. This results in full-channel gating and leads to the highest low-frequency voltage gain reported so far in top-gated CVD graphene devices operating in air ambient, A(v) ∼ -5. Such gain enabled logic inverters with the same voltage swing of 0.56 V at their input and output. Graphene inverters could find their way in realistic applications where high-speed operation is desired but power dissipation is not a concern, similar to emitter-coupled logic.

Determination of work function of graphene under a metal electrode and its role in contact resistance

Although the work function of graphene under a given metal electrode is critical information for the realization of high-performance graphene-based electronic devices, relatively little relevant research has been carried out to date. In this work, the work function values of graphene under various metals are accurately measured for the first time through a detailed analysis of the capacitance-voltage (C-V) characteristics of a metal-graphene-oxide-semiconductor (MGOS) capacitor structure. In contrast to the high work function of exposed graphene of 4.89-5.16 eV, the work function of graphene under a metal electrode varies depending on the metal species. With a Cr/Au or Ni contact, the work function of graphene is pinned to that of the contacted metal, whereas with a Pd or Au contact the work function assumes a value of ∼4.62 eV regardless of the work function of the contact metal. A study of the gate voltage dependence on the contact resistance shows that the latter case provides lower contact resistance.

All graphene-based thin film transistors on flexible plastic substrates

High-performance, flexible all graphene-based thin film transistor (TFT) was fabricated on plastic substrates using a graphene active layer, graphene oxide (GO) dielectrics, and graphene electrodes. The GO dielectrics exhibit a dielectric constant (3.1 at 77 K), low leakage current (17 mA/cm(2)), breakdown bias (1.5 × 10(6) V/cm), and good mechanical flexibility. Graphene-based TFTs showed a hole and electron mobility of 300 and 250 cm(2)/(V·s), respectively, at a drain bias of -0.1 V. Moreover, graphene TFTs on the plastic substrates exhibited remarkably good mechanical flexibility and optical transmittance. This method explores a significant step for the application of graphene toward flexible and stretchable electronics.

High mobility flexible graphene field-effect transistors with self-healing gate dielectrics

A high-mobility low-voltage graphene field-effect transistor (FET) array was fabricated on a flexible plastic substrate using high-capacitance natural aluminum oxide as a gate dielectric in a self-aligned device configuration. The high capacitance of the native aluminum oxide and the self-alignment, which minimizes access resistance, yield a high current on/off ratio and an operation voltage below 3 V, along with high electron and hole mobility of 230 and 300 cm(2)/V·s, respectively. Moreover, the native aluminum oxide is resistant to mechanical bending and exhibits self-healing upon electrical breakdown. These results indicate that self-aligned graphene FETs can provide remarkably improved device performance and stability for a range of applications in flexible electronics.

Self-aligned fabrication of graphene RF transistors with T-shaped gate

Exceptional electronic properties of graphene make it a promising candidate as a material for next generation electronics; however, self-aligned fabrication of graphene transistors has not been fully explored. In this paper, we present a scalable method for fabrication of self-aligned graphene transistors by defining a T-shaped gate on top of graphene, followed by self-aligned source and drain formation by depositing Pd with the T-gate as a shadow mask. This transistor design provides significant advantages such as elimination of misalignment, reduction of access resistance by minimizing ungated graphene, and reduced gate charging resistance. To achieve high-yield scalable fabrication, we have combined the use of large-area graphene synthesis by chemical vapor deposition, wafer-scale transfer, and e-beam lithography to deposit T-shaped top gates. The fabricated transistors with channel lengths in the range of 110-170 nm exhibited excellent performance with peak current density of 1.3 mA/μm and peak transconductance of 0.5 mS/μm, which is one of the highest transconductance values reported. In addition, the T-gate design enabled us to achieve graphene transistors with extrinsic current-gain cutoff frequency of 23 GHz and maximum oscillation frequency of 10 GHz. These results represent important steps toward self-aligned design of graphene transistors for various applications.

Origin of the relatively low transport mobility of graphene grown through chemical vapor deposition

The reasons for the relatively low transport mobility of graphene grown through chemical vapor deposition (CVD-G), which include point defect, surface contamination, and line defect, were analyzed in the current study. A series of control experiments demonstrated that the determinant factor for the low transport mobility of CVD-G did not arise from point defects or surface contaminations, but stemmed from line defects induced by grain boundaries. Electron microscopies characterized the presence of grain boundaries and indicated the polycrystalline nature of the CVD-G. Field-effect transistors based on CVD-G without the grain boundary obtained a transport mobility comparative to that of Kish graphene, which directly indicated the detrimental effect of grain boundaries. The effect of grain boundary on transport mobility was qualitatively explained using a potential barrier model. Furthermore, the conduction mechanism of CVD-G was also investigated using the temperature dependence measurements. This study can help understand the intrinsic transport features of CVD-G.

Graphene: nanoscale processing and recent applications

One of the most interesting features of graphene is the rich physics set up by the various nanostructures it may adopt. The planar structure of graphene makes this material ideal for patterning at the nanoscale. The breathtakingly fast evolution of research on graphene growth and preparation methods has made possible the preparation of samples with arbitrary sizes. Available sample production techniques, combined with the right patterning tools, can be used to tailor the graphene sheet into functional nanostructures, even whole electronic circuits. This paper is a review of the existing graphene patterning techniques and potential applications of related lithographic methods.

Integrated circuits and logic operations based on single-layer MoS2

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

Ambipolar to unipolar conversion in graphene field-effect transistors

Typical graphene field-effect transistors (GFETs) show ambipolar conduction that is unfavorable for some electronic applications. In this work, we report on the development of unipolar GFETs. We found that the titanium oxide situated on the graphene surface induced significant hole doping. The threshold voltage of the unipolar p-type GFET was tunable by varying the density of the attached titanium oxide through an etching process. An annealing process followed by silicon nitride passivation was found to convert the p-type GFETs to unipolar n-type GFETs. An air-stable complementary inverter integrated from the p- and n-GFETs was also successfully demonstrated. The simple fabrication processes are compatible with the conventional CMOS manufacturing technology.

Formation of bilayer bernal graphene: layer-by-layer epitaxy via chemical vapor deposition

We report the epitaxial formation of bilayer Bernal graphene on copper foil via chemical vapor deposition. The self-limit effect of graphene growth on copper is broken through the introduction of a second growth process. The coverage of bilayer regions with Bernal stacking can be as high as 67% before further optimization. Facilitated with the transfer process to silicon/silicon oxide substrates, dual-gated graphene transistors of the as-grown bilayer Bernal graphene were fabricated, showing typical tunable transfer characteristics under varying gate voltages. The high-yield layer-by-layer epitaxy scheme will not only make this material easily accessible but reveal the fundamental mechanism of graphene growth on copper.

Enhanced logic performance with semiconducting bilayer graphene channels

Realization of logic circuits in graphene with an energy gap (EG) remains one of the main challenges for graphene electronics. We found that large transport EGs (>100 meV) can be fulfilled in dual-gated bilayer graphene underneath a simple alumina passivation top gate stack, which directly contacts the graphene channels without an inserted buffer layer. With the presence of EGs, the electrical properties of the graphene transistors are significantly enhanced, as manifested by enhanced on/off current ratio, subthreshold slope, and current saturation. For the first time, complementary-like semiconducting logic graphene inverters are demonstrated that show a large improvement over their metallic counterparts. This result may open the way for logic applications of gap-engineered graphene.

Epitaxial chemical vapor deposition growth of single-layer graphene over cobalt film crystallized on sapphire

Epitaxial chemical vapor deposition (CVD) growth of uniform single-layer graphene is demonstrated over Co film crystallized on c-plane sapphire. The single crystalline Co film is realized on the sapphire substrate by optimized high-temperature sputtering and successive H(2) annealing. This crystalline Co film enables the formation of uniform single-layer graphene, while a polycrystalline Co film deposited on a SiO(2)/Si substrate gives a number of graphene flakes with various thicknesses. Moreover, an epitaxial relationship between the as-grown graphene and Co lattice is observed when synthesis occurs at 1000 °C; the direction of the hexagonal lattice of the single-layer graphene completely matches with that of the underneath Co/sapphire substrate. The orientation of graphene depends on the growth temperature and, at 900 °C, the graphene lattice is rotated at 22 ± 8° with respect to the Co lattice direction. Our work expands a possibility of synthesizing single-layer graphene over various metal catalysts. Moreover, our CVD growth gives a graphene film with predefined orientation, and thus can be applied to graphene engineering, such as cutting along a specific crystallographic direction, for future electronics applications.