Nanoporous silicon oxide memory

Filament-free memristors for computing

Memristors have attracted increasing attention due to their tremendous potential to accelerate data-centric computing systems. The dynamic reconfiguration of memristive devices in response to external electrical stimuli can provide highly desirable novel functionalities for computing applications when compared with conventional complementary-metal-oxide-semiconductor (CMOS)-based devices. Those most intensively studied and extensively reviewed memristors in the literature so far have been filamentary type memristors, which typically exhibit a relatively large variability from device to device and from switching cycle to cycle. On the other hand, filament-free switching memristors have shown a better uniformity and attractive dynamical properties, which can enable a variety of new computing paradigms but have rarely been reviewed. In this article, a wide range of filament-free switching memristors and their corresponding computing applications are reviewed. Various junction structures, switching properties, and switching principles of filament-free memristors are surveyed and discussed. Furthermore, we introduce recent advances in different computing schemes and their demonstrations based on non-filamentary memristors. This Review aims to present valuable insights and guidelines regarding the key computational primitives and implementations enabled by these filament-free switching memristors.

3D-structured mesoporous silica memristors for neuromorphic switching and reservoir computing

Memristors are emerging as promising candidates for practical application in reservoir computing systems that are capable of temporal information processing. Here, we experimentally implement a physical reservoir computing system using resistive memristors based on three-dimensional (3D)-structured mesoporous silica (mSiO₂) thin films fabricated by a low cost, fast and vacuum-free sol-gel technique. The in situ learning capability and a classification accuracy of 100% on a standard machine learning dataset are experimentally demonstrated. The volatile (temporal) resistive switching in diffusive memristors arises from the formation and subsequent spontaneous rupture of conductive filaments via diffusion of Ag species within the 3D-structured nanopores of the mSiO₂ thin film. Besides volatile switching, the devices also exhibit a bipolar non-volatile resistive switching behavior when the devices are operated at a higher compliance current level. The implementation of mSiO₂ thin films opens the route to fabricate a simple and low cost dynamic memristor with a temporal information process functionality, which is essential for neuromorphic computing applications.

The unrevealed 3D morphological evolution of annealed nanoporous thin films

Nanoporous materials (sub-10 nm in diameter) have potential applications in chips, biosensors, thermoelectrics, desalination and other fields due to their large surface-to-volume ratio. Thermal annealing is a preferred technique to precisely control the ultra-fine nanopore size. Here, the 3D morphological evolution of a membrane with periodic nanopores by thermal annealing is studied. It is found that the evolution is determined by the combination of the membrane thickness, the initial nanopore radius and the periodic length of the porous pattern, rather than the previously suggested ratio between the membrane thickness and pore radius. High-temperature annealing experiments and molecular dynamics simulations are performed to confirm the rationality of the newly proposed model. Energy analysis demonstrates that surface energy minimization is the driving force of the morphological evolution. The local minimum of energy in the new model provides the possibility of thermal stability of nanoporous silicon as a thermoelectric material. This study provides guidance for the mass production of nanoporous membranes with high-temperature annealing.

Transparent, Flexible, and Low-Operating-Voltage Resistive Switching Memory Based on Al2O3/IZO Multilayer

In this study, a different number of indium zinc oxide (IZO) interlayers are fabricated into Al₂O₃-based transparent resistive switching memory on a transparent indium tin oxide (ITO)/glass substrate at room temperature. Al₂O₃/IZO multilayer transparent memory has a transmittance of at least 65% in the wavelength range of 400-900 nm. In addition, the Al₂O₃/IZO multilayer transparent memory can achieve an electroforming voltage that is 35.7% lower than that of ITO/pure-Al₂O₃/IZO transparent memory. The fabricated Al₂O₃/IZO multilayer transparent memory exhibits typical bipolar resistive switching behavior, regardless of the number of IZO interlayers. Also, the fabricated Al₂O₃/IZO multilayer transparent memory has a low operating voltage within ±1.5 V. In addition, a flexible Al₂O₃/IZO multilayer transparent memory is fabricated using the same process on ITO-coated polyethylene terephthalate. The fabricated flexible transparent memory also maintains the resistive switching characteristics during the bending state.

Controlling resistive switching behavior in the solution processed SiO2-x device by the insertion of TiO2 nanoparticles

The resistive switching behavior of the solution processed SiO_x device was investigated by inserting TiO₂ nanoparticles (NPs). Compared to the pristine SiO_x device, the TiO₂ NPs inserted SiO_x (SiO_x@TiO₂ NPs) device achieves outstanding switching characteristics, namely a higher ratio of SET/RESET, lower operating voltages, improved cycle-to-cycle variability, faster switching speed, and multiple-RESET states. Density functional theory calculation (DFT) and circuit breaker simulation (CB) were used to detail the origin of the outstanding switching characteristic of the SiO_x@TiO₂ NPs. The improvement in resistive switching is mainly based on the difference in formation/rupture of the conductive path in the SiO₂ and SiO₂@TiO₂ NPs devices. In particular, the reduction of resistance and lower switching voltage of TiO₂ NPs control the formation and rupture of the conductive path to achieve more abrupt switching between SET/RESET with higher on/off ratio. This method of combined DFT calculation and CB offers a promising approach for high-performance non-volatile memory applications.

Flexible Neural Network Realized by the Probabilistic SiOx Memristive Synaptic Array for Energy-Efficient Image Learning

The human brain's neural networks are sparsely connected via tunable and probabilistic synapses, which may be essential for performing energy-efficient cognitive and intellectual functions. In this sense, the implementation of a flexible neural network with probabilistic synapses is a first step toward realizing the ultimate energy-efficient computing framework. Here, inspired by the efficient threshold-tunable and probabilistic rod-to-rod bipolar synapses in the human visual system, a 16 × 16 crossbar array comprising the vertical form of gate-tunable probabilistic SiO_x memristive synaptic barristor utilizing the Si/graphene heterojunction is designed and fabricated. Controllable stochastic switching dynamics in this array are achieved via various input voltage pulse schemes. In particular, the threshold tunability via electrostatic gating enables the efficient in situ alteration of the probabilistic switching activation (P_Act ) from 0 to 1.0, and can even modulate the degree of the P_Act change. A drop-connected algorithm based on the P_Act is constructed and used to successfully classify the shapes of several fashion items. The suggested approach can decrease the learning energy by up to ≈2,116 times relative to that of the conventional all-to-all connected network while exhibiting a high recognition accuracy of ≈93 %.

Controllable SiOx Nanorod Memristive Neuron for Probabilistic Bayesian Inference

Modern artificial neural network technology using a deterministic computing framework is faced with a critical challenge in dealing with massive data that are largely unstructured and ambiguous. This challenge demands the advances of an elementary physical device for tackling these uncertainties. Here, we designed and fabricated a SiO_x nanorod memristive device by employing the glancing angle deposition (GLAD) technique, suggesting a controllable stochastic artificial neuron that can mimic the fundamental integrate-and-fire signaling and stochastic dynamics of a biological neuron. The nanorod structure provides the random distribution of multiple nanopores all across the active area, capable of forming a multitude of Si filaments at many SiO_x nanorod edges after the electromigration process, leading to a stochastic switching event with very high dynamic range (≈5.15 × 10¹⁰ ) and low energy (≈4.06 pJ). Different probabilistic activation (ProbAct) functions in a sigmoid form are implemented, showing its controllability with low variation by manufacturing and electrical programming schemes. Furthermore, as an application prospect, based on the suggested memristive neuron, we demonstrated the self-resting neural operation with the local circuit configuration and revealed probabilistic Bayesian inferences for genetic regulatory networks with low normalized mean squared errors (≈2.41 × 10^-2 ) and its robustness to the ProbAct variation.

Standards for the Characterization of Endurance in Resistive Switching Devices

Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >10⁶ cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products.

Nanoporous Dielectric Resistive Memories Using Sequential Infiltration Synthesis

Resistance switching in metal-insulator-metal structures has been extensively studied in recent years for use as synaptic elements for neuromorphic computing and as nonvolatile memory elements. However, high switching power requirements, device variabilities, and considerable trade-offs between low operating voltages, high on/off ratios, and low leakage have limited their utility. In this work, we have addressed these issues by demonstrating the use of ultraporous dielectrics as a pathway for high-performance resistive memory devices. Using a modified atomic layer deposition based technique known as sequential infiltration synthesis, which was developed originally for improving polymer properties such as enhanced etch resistance of electron-beam resists and for the creation of films for filtration and oleophilic applications, we are able to create ∼15 nm thick ultraporous (pore size ∼5 nm) oxide dielectrics with up to 73% porosity as the medium for filament formation. We show, using the Ag/Al₂O₃ system, that the ultraporous films result in ultrahigh on/off ratio (>10⁹) at ultralow switching voltages (∼±600 mV) that are 10× smaller than those for the bulk case. In addition, the devices demonstrate fast switching, pulsed endurance up to 1 million cycles. and high temperature (125 °C) retention up to 10⁴ s, making this approach highly promising for large-scale neuromorphic and memory applications. Additionally, this synthesis methodology provides a compatible, inexpensive route that is scalable and compatible with existing semiconductor nanofabrication methods and materials.

Silicon oxide-niobium oxide mixture films and nanolaminates grown by atomic layer deposition from niobium pentaethoxide and hexakis(ethylamino) disilane

Amorphous SiO₂-Nb₂O₅ nanolaminates and mixture films were grown by atomic layer deposition. The films were grown at 300 °C from Nb(OC₂H₅)₅, Si₂(NHC₂H₅)₆, and O₃ to thicknesses ranging from 13 to 130 nm. The niobium to silicon atomic ratio was varied in the range of 0.11-7.20. After optimizing the composition, resistive switching properties could be observed in the form of characteristic current-voltage behavior. Switching parameters in the conventional regime were well defined only in a SiO₂:Nb₂O₅ mixture at certain, optimized, composition with Nb:Si atomic ratio of 0.13, whereas low-reading voltage measurements allowed recording memory effects in a wider composition range.

Silicon Oxide (SiOx ): A Promising Material for Resistance Switching?

Interest in resistance switching is currently growing apace. The promise of novel high-density, low-power, high-speed nonvolatile memory devices is appealing enough, but beyond that there are exciting future possibilities for applications in hardware acceleration for machine learning and artificial intelligence, and for neuromorphic computing. A very wide range of material systems exhibit resistance switching, a number of which-primarily transition metal oxides-are currently being investigated as complementary metal-oxide-semiconductor (CMOS)-compatible technologies. Here, the case is made for silicon oxide, perhaps the most CMOS-compatible dielectric, yet one that has had comparatively little attention as a resistance-switching material. Herein, a taxonomy of switching mechanisms in silicon oxide is presented, and the current state of the art in modeling, understanding fundamental switching mechanisms, and exciting device applications is summarized. In conclusion, silicon oxide is an excellent choice for resistance-switching technologies, offering a number of compelling advantages over competing material systems.

Pseudohalide-Induced 2D (CH3 NH3 )2 PbI2 (SCN)2 Perovskite for Ternary Resistive Memory with High Performance

Recently, organic-inorganic hybrid perovskites (OIHP) are studied in memory devices, but ternary resistive memory with three states based on OIHP is not achieved yet. In this work, ternary resistive memory based on hybrid perovskite is achieved with a high device yield (75%), much higher than most organic ternary resistive memories. The pseudohalide-induced 2D (CH₃ NH₃ )₂ PbI₂ (SCN)₂ perovskite thin film is prepared by using a one-step solution method and fabricated into Al/perovskite film/indium-tin oxide (glass substrate as well as flexible polyethylene terephthalate substrate) random resistive access memory (RRAM) devices. The three states have a conductivity ratio of 1:10³ :10⁷ , long retention over 10 000 s, and good endurance properties. The electrode area variation, impedance test, and current-voltage plotting show that the two resistance switches are attributable to the charge trap filling due to the effect of unscreened defect in 2D nanosheets and the formation of conductive filaments, respectively. This work paves way for stable perovskite multilevel RRAMs in ambient atmosphere.

Controllable Switching Filaments Prepared via Tunable and Well-Defined Single Truncated Conical Nanopore Structures for Fast and Scalable SiOx Memory

The controllability of switching conductive filaments is one of the central issues in the development of reliable metal-oxide resistive memory because the random dynamic nature and formation of the filaments pose an obstacle to desirable switching performance. Here, we introduce a simple and novel approach to control and form a single silicon nanocrystal (Si-NC) filament for use in SiO_x memory devices. The filament is formed with a confined vertical nanoscale gap by using a well-defined single vertical truncated conical nanopore (StcNP) structure. The physical dimensions of the Si-NC filaments such as number, size, and length, which have a significant influence on the switching properties, can be simply engineered by the breakdown of an Au wire through different StcNP structures. In particular, we demonstrate that the designed SiO_x memory junction with a StcNP of pore depth of ∼75 nm and a bottom diameter of ∼10 nm exhibited a switching speed of up to 6 ns for both set and reset process, significantly faster than reported SiO_x memory devices. The device also exhibited a high ON-OFF ratio, multistate storage ability, acceptable endurance, and retention stability. The influence of the physical dimensions of the StcNP on the switching features is discussed based on the simulated temperature profiles of the Au wire and the nanogap size generated inside the StcNP structure during electromigration.

Reliable Multistate Data Storage with Low Power Consumption by Selective Oxidation of Pyramid-Structured Resistive Memory

Multilevel data storage using resistive random access memory (RRAM) has attracted significant attention for addressing the challenges associated with the rapid advances in information technologies. However, it is still difficult to secure reliable multilevel resistive switching of RRAM due to the stochastic and multiple formation of conductive filaments (CFs). Herein, we demonstrate that a single CF, derived from selective oxidation by a structured Cu active electrode, can solve the reliability issue. High-quality pyramidal Cu electrodes with a sharp tip are prepared via the template-stripping method. Morphology-dependent surface energy facilitates the oxidation of Cu atoms at the tip rather than in other regions, and the tip-enhanced electric fields can accelerate the transport of the generated Cu ions. As a result, CF growth occurs mainly at the tip of the pyramidal electrode, which is confirmed by high-resolution electron microscopy and elemental analysis. The RRAM exhibits highly uniform and low forming voltages (the average forming voltage and its standard deviation for 20 pyramid-based RRAMs are 0.645 and 0.072 V, respectively). Moreover, all multilevel resistance states for the RRAMs are clearly distinguished and show narrow distributions within 1 order of magnitude, leading to reliable cell-to-cell performance for MLC operation.

Intrinsic Resistance Switching in Amorphous Silicon Suboxides: The Role of Columnar Microstructure

We studied intrinsic resistance switching behaviour in sputter-deposited amorphous silicon suboxide (a-SiO_x) films with varying degrees of roughness at the oxide-electrode interface. By combining electrical probing measurements, atomic force microscopy (AFM), and scanning transmission electron microscopy (STEM), we observe that devices with rougher oxide-electrode interfaces exhibit lower electroforming voltages and more reliable switching behaviour. We show that rougher interfaces are consistent with enhanced columnar microstructure in the oxide layer. Our results suggest that columnar microstructure in the oxide will be a key factor to consider for the optimization of future SiOx-based resistance random access memory.

Surface engineering to achieve organic ternary memory with a high device yield and improved performance

Organic memories fabricated on surface-engineered indium tin oxide show the highest ternary yield (82%) to date and better performance.

Squaraine molecules deposited on indium tin oxide (ITO) substrates modified with phosphonic acids crystalize more orderly than do those on untreated ITO. The as-fabricated electro-resistive memories show the highest ternary device yield observed to date (82%), a narrower switching voltage distribution, and better retention as well as resistance uniformity.

Reliable Memristive Switching Memory Devices Enabled by Densely Packed Silver Nanocone Arrays as Electric-Field Concentrators

Memristor devices based on electrochemical metallization operate through electrochemical formation/dissolution of nanoscale metallic filaments, and they are considered a promising future nonvolatile memory because of their outstanding characteristics over conventional charge-based memories. However, nanoscale conductive paths or filaments precipitated from the redox process of metallic elements are randomly formed inside oxides, resulting in unexpected and stochastic memristive switching parameters including the operating voltage and the resistance state. Here, we present the guided formation of conductive filaments in Ag nanocone/SiO₂ nanomesh/Pt memristors fabricated by high-resolution nanotransfer printing. Consequently, the uniformity of the memristive switching behavior is significantly improved by the existence of electric-field concentrator arrays consisting of Ag nanocones embedded in SiO₂ nanomesh structures. This selective and controlled filament growth was experimentally supported by analyzing simultaneously the surface morphology and current-mapping results using conductive atomic force microscopy. Moreover, stable multilevel switching operations with four discrete conduction states were achieved by the nanopatterned memristor device, demonstrating its potential in high-density nanoscale memory devices.

Flexible Nanoporous WO3-x Nonvolatile Memory Device

Flexible resistive random access memory (RRAM) devices have attracted great interest for future nonvolatile memories. However, making active layer films at high temperature can be a hindrance to RRAM device fabrication on flexible substrates. Here, we introduced a flexible nanoporous (NP) WO3-x RRAM device using anodic treatment in a room-temperature process. The flexible NP WO3-x RRAM device showed bipolar switching characteristics and a high ION/IOFF ratio of ∼10(5). The device also showed stable retention time over 5 × 10(5) s, outstanding cell-to-cell uniformity, and bending endurance over 10(3) cycles when measured in both the flat and the maximum bending conditions.

Nanoporous SiO2 thin films made by atomic layer deposition and atomic etching

A new route to prepare nanoporous SiO2 films by mixing atomic-layer-deposited alumina and silica in an Å-scale is presented. The selective removal of Al2O3 from the composites using wet chemical etching with phosphoric acid resulted in nanoporous thin SiO2 layers. A diffusion-controlled dissolution mechanism is identified whereby an interesting reorganization of the residual SiO2 is observed. The atomic scale oxide mixing is decisive in attaining and tailoring the film porosity. The porosity and the refractive index of nanoporous silica films were tailored from 9% to 69% and from 1.40 to 1.13, respectively. The nanoporous silica was successfully employed as antireflection coatings and as diffusion membranes to encapsulate nanostructures.

Epitaxial Brownmillerite Oxide Thin Films for Reliable Switching Memory

Resistive switching memory, which is mostly based on polycrystalline thin films, suffers from wide distributions in switching parameters-including set voltage, reset voltage, and resistance-in their low- and high-resistance states. One of the most commonly used methods to overcome this limitation is to introduce inhomogeneity. By contrast, in this paper, we obtained uniform resistive switching parameters and sufficiently low forming voltage by maximizing the uniformity of an epitaxial thin film. To achieve this result, we deposited an SrFeOx/SrRuO3 heteroepitaxial structure onto an SrTiO3 (001) substrate by pulsed laser deposition, and then we deposited an Au top electrode by electron-beam evaporation. This device exhibited excellent bipolar resistance switching characteristics, including a high on/off ratio, narrow distribution of key switching parameters, and long data retention time. We interpret these phenomena in terms of a local, reversible phase transformation in the SrFeOx film between brownmillerite and perovskite structures. Using the brownmillerite structure and atomically uniform thickness of the heteroepitaxial SrFeOx thin film, we overcame two major hurdles in the development of resistive random-access memory devices: high forming voltage and broad distributions of switching parameters.

Creating nanoporosity in silver nanocolumns by direct exposure to radio-frequency air plasma

Nanoporous materials are of great importance for a broad range of applications including catalysis, optical sensors and water filtration. Although several approaches already exist for the creation of nanoporous materials, the race for the development of versatile methods, more suitable for the nanoelectronics industry, is still ongoing. In this communication we report for the first time on the possibility of generating nanoporosity in silver nanocolumns using a dry approach based on the oxidation of silver by direct exposure to a commercially available radio-frequency air plasma. The silver nanocolumns are created by glancing angle deposition using magnetron sputtering of a silver target in pure argon plasma. We show that upon exposure to the rf air plasma, the nanocolumns transform from solid silver into nanoporous silver oxide. We further show that by tuning the plasma pressure and the exposure duration, the oxidation process can be finely adjusted allowing for precisely controlling the morphology and the nanoporosity of the silver oxide nanocolumns. The generation of porosity within the silver nanocolumns is explained according to a cracking-induced oxidation mechanism based on two repeated events occurring alternately during the oxidation process: (i) oxidation of silver upon exposure to the air plasma and (ii) generation of nanocracks and blisters within the oxide layer due to the high internal stress generated within the material during oxidation.

Tunable charge-trap memory based on few-layer MoS2

Charge-trap memory with high-κ dielectric materials is considered to be a promising candidate for next-generation memory devices. Ultrathin layered two-dimensional (2D) materials like graphene and MoS2 have been receiving much attention because of their fantastic physical properties and potential applications in electronic devices. Here, we report on a dual-gate charge-trap memory device composed of a few-layer MoS2 channel and a three-dimensional (3D) Al2O3/HfO2/Al2O3 charge-trap gate stack. Because of the extraordinary trapping ability of both electrons and holes in HfO2, the MoS2 memory device exhibits an unprecedented memory window exceeding 20 V. Importantly, with a back gate the window size can be effectively tuned from 15.6 to 21 V; the program/erase current ratio can reach up to 10(4), allowing for multibit information storage. Moreover, the device shows a high endurance of hundreds of cycles and a stable retention of ∼ 28% charge loss after 10 years, which is drastically lower than ever reported MoS2 flash memory. The combination of 2D materials with traditional high-κ charge-trap gate stacks opens up an exciting field of nonvolatile memory devices.

Chemically-derived CuO/In2O3-based nanocomposite for diode applications

The potential of CuO-based nanocomposite synthesized through a facile surfactant-free wet chemical strategy has been demonstrated for photoelectronic applications.