Impact of device scaling on the electrical properties of MoS2 field-effect transistors

Influence of High-κ Dielectrics Integration on ALD-Based MoS2 Field-Effect Transistor Performance

The integration of high-κ dielectrics on MoS2 field-effect transistors (FETs) is essential for the realization of MoS2 in ultrascaled nanoelectronic devices and circuits. Most studies covering this topic are based on exfoliated MoS2 flakes or chemical vapor deposition (CVD) grown MoS2 films, whereas other techniques, such as atomic layer deposition (ALD), are also gaining attention for the growth of MoS2 in recent years. In this work, we grow large-area MoS2 by means of plasma-enhanced (PE-)ALD and evaluate the influence of high-κ dielectrics on the properties of ALD-based MoS2 FETs through electrical characterization combined with surface-chemical and high-resolution scanning transmission electron microscopy (HR-STEM) analyses. We grow HfO x , AlO x , or both by means of PE-ALD or thermal ALD on our fabricated devices and show that, in addition to the dielectric constant, three other major parameters related to the processing of the dielectrics can simultaneously affect the MoS2 FET electrical characteristics and govern its doping. These parameters are the stoichiometry of the dielectric, its carbon impurity content, and the degree to which the MoS2 surface oxidizes upon the dielectric growth. When grown at 100 °C, our HfO x films are oxygen-vacant whereas our AlO x films are oxygen-rich. In addition, carbon impurities are incorporated into the dielectrics at low deposition temperatures, being one of the likely causes of the MoS2 FET overall n-type performance in all of the studied cases. Our investigations also reveal that PE-ALD of HfO x or AlO x oxidizes the MoS2 surface, whereas thermal ALD AlO x leaves MoS2 almost intact. In this respect, if thermal ALD AlO x of proper thickness is grown between MoS2 and HfO x , it can reduce the degree to which the MoS2 surface oxidizes by HfO x and meanwhile improve the total dielectric constant, altogether leading to the most optimal electrical performance in ALD-based MoS2 FETs.

Innovations of metallic contacts on semiconducting 2D transition metal dichalcogenides toward advanced 3D-structured field-effect transistors

2D semiconductors, represented by transition metal dichalcogenides (TMDs), have the potential to be alternative channel materials for advanced 3D field-effect transistors, such as gate-all-around field-effect-transistors (GAAFETs) and complementary field-effect-transistors (C-FETs), due to their inherent atomic thinness, moderate mobility, and short scaling lengths. However, 2D semiconductors encounter several technological challenges, especially the high contact resistance issue between 2D semiconductors and metals. This review provides a comprehensive overview of the high contact resistance issue in 2D semiconductors, including its physical background and the efforts to address it, with respect to their applicability to GAAFET structures.

Gamma-Irradiation-Induced Electrical Characteristic Variations in MoS2 Field-Effect Transistors with Buried Local Back-Gate Structure

The impact of radiation on MoS2-based devices is an important factor in the utilization of two-dimensional semiconductor-based technology in radiation-sensitive environments. In this study, the effects of gamma irradiation on the electrical variations in MoS2 field-effect transistors with buried local back-gate structures were investigated, and their related effects on Al2O3 gate dielectrics and MoS2/Al2O3 interfaces were also analyzed. The transfer and output characteristics were analyzed before and after irradiation. The current levels decreased by 15.7% under an exposure of 3 kGy. Additionally, positive shifts in the threshold voltages of 0.50, 0.99, and 1.15 V were observed under irradiations of 1, 2, and 3 kGy, respectively, compared to the non-irradiated devices. This behavior is attributable to the comprehensive effects of hole accumulation in the Al2O3 dielectric interface near the MoS2 side and the formation of electron trapping sites at the interface, which increased the electron tunneling at the MoS2 channel/dielectric interface.

Impact of Rh, Ru, and Pd Leads and Contact Topologies on Performance of WSe2 FETs: A First Comparative Ab Initio Study

2D field-effect transistors (FETs) fabricated with transition metal dichalcogenide (TMD) materials are a potential replacement for the silicon-based CMOS. However, the lack of advancement in p-type contact is also a key factor hindering TMD-based CMOS applications. The less investigated path towards improving electrical characteristics based on contact geometries with low contact resistance (RC) has also been established. Moreover, finding contact metals to reduce the RC is indeed one of the significant challenges in achieving the above goal. Our research provides the first comparative analysis of the three contact configurations for a WSe2 monolayer with different noble metals (Rh, Ru, and Pd) by employing ab initio density functional theory (DFT) and non-equilibrium Green's function (NEGF) methods. From the perspective of the contact topologies, the RC and minimum subthreshold slope (SSMIN) of all the conventional edge contacts are outperformed by the novel non-van der Waals (vdW) sandwich contacts. These non-vdW sandwich contacts reveal that their RC values are below 50 Ω∙μm, attributed to the narrow Schottky barrier widths (SBWs) and low Schottky barrier heights (SBHs). Not only are the RC values dramatically reduced by such novel contacts, but the SSMIN values are lower than 68 mV/dec. The new proposal offers the lowest RC and SSMIN, irrespective of the contact metals. Further considering the metal leads, the WSe2/Rh FETs based on the non-vdW sandwich contacts show a meager RC value of 33 Ω∙μm and an exceptional SSMIN of 63 mV/dec. The two calculated results present the smallest-ever values reported in our study, indicating that the non-vdW sandwich contacts with Rh leads can attain the best-case scenario. In contrast, the symmetric convex edge contacts with Pd leads cause the worst-case degradation, yielding an RC value of 213 Ω∙μm and an SSMIN value of 95 mV/dec. While all the WSe2/Ru FETs exhibit medium performances, the minimal shift in the transfer curves is interestingly advantageous to the circuit operation. Conclusively, the low-RC performances and the desirable SSMIN values are a combination of the contact geometries and metal leads. This innovation, achieved through noble metal leads in conjunction with the novel contact configurations, paves the way for a TMD-based CMOS with ultra-low RC and rapid switching speeds.

Self-Expansion Based Multi-Patterning for 2D Materials Fabrication beyond the Lithographical Limit

Two-dimensional (2D) materials are promising successors for silicon transistor channels in ultimately scaled devices, necessitating significant research efforts to study their behavior at nanoscopic length scales. Unfortunately, current research has limited itself to direct patterning approaches, which limit the achievable resolution to the diffraction limit and introduce unwanted defects into the 2D material. The potential of multi-patterning to fabricate 2D materials features with unprecedented precision and low complexity at large scale is demonstrated here. By combining lithographic patterning of a mandrel and bottom-up self-expansion, this approach enables pattern resolution one order of magnitude below the lithographical resolution. In-depth characterization of the self-expansion double patterning (SEDP) process reveals the ability to manipulate the critical dimension with nanometer precision through a self-limiting and temperature-controlled oxidation process. These results indicate that the SEDP process can regain the quality and morphology of the 2D material, as shown by high-resolution microscopy and optical spectroscopy. This approach is shown to open up new avenues for research into high-performance, ultra-scaled 2D materials devices for future electronics.

Three-dimensional integration of two-dimensional field-effect transistors

In the field of semiconductors, three-dimensional (3D) integration not only enables packaging of more devices per unit area, referred to as 'More Moore'1 but also introduces multifunctionalities for 'More than Moore'2 technologies. Although silicon-based 3D integrated circuits are commercially available3-5, there is limited effort on 3D integration of emerging nanomaterials6,7 such as two-dimensional (2D) materials despite their unique functionalities7-10. Here we demonstrate (1) wafer-scale and monolithic two-tier 3D integration based on MoS2 with more than 10,000 field-effect transistors (FETs) in each tier; (2) three-tier 3D integration based on both MoS2 and WSe2 with about 500 FETs in each tier; and (3) two-tier 3D integration based on 200 scaled MoS2 FETs (channel length, LCH = 45 nm) in each tier. We also realize a 3D circuit and demonstrate multifunctional capabilities, including sensing and storage. We believe that our demonstrations will serve as the foundation for more sophisticated, highly dense and functionally divergent integrated circuits with a larger number of tiers integrated monolithically in the third dimension.

Landauer-QFLPS Model for Mixed Schottky-Ohmic Contact Two-Dimensional Transistors

Two-dimensional material-based field-effect transistors (2DM-FETs) are playing a revolutionary role in electronic devices. However, before electronic design automation (EDA) for 2DM-FETs can be achieved, it remains necessary to determine how to incorporate contact transports into model. Reported methods compromise between physical intelligibility and model compactness due to the heterojunction nature. To address this, quasi-Fermi-level phase space theory (QFLPS) is generalized to incorporate contact transports using the Landauer formula. It turns out that the Landauer-QFLPS model effectively overcomes the issue of concern. The proposed new formula can describe 2DM-FETs with Schottky or Ohmic contacts with superior accuracy and efficiency over previous methods, especially when describing non-monotonic drain conductance characteristics. A three-bit threshold inverter quantizer (TIQ) circuit is fabricated using ambipolar black phosphorus and it is demonstrated that the model accurately predicts circuit performance. The model could be very effective and valuable in the development of 2DM-FET-based integrated circuits.

Toward High-Performance p-Type Two-Dimensional Field Effect Transistors: Contact Engineering, Scaling, and Doping

n-type field effect transistors (FETs) based on two-dimensional (2D) transition-metal dichalcogenides (TMDs) such as MoS2 and WS2 have come close to meeting the requirements set forth in the International Roadmap for Devices and Systems (IRDS). However, p-type 2D FETs are dramatically lagging behind in meeting performance standards. Here, we adopt a three-pronged approach that includes contact engineering, channel length (Lch) scaling, and monolayer doping to achieve high performance p-type FETs based on synthetic WSe2. Using electrical measurements backed by atomistic imaging and rigorous analysis, Pd was identified as the favorable contact metal for WSe2 owing to better epitaxy, larger grain size, and higher compressive strain, leading to a lower Schottky barrier height. While the ON-state performance of Pd-contacted WSe2 FETs was improved by ∼10× by aggressively scaling Lch from 1 μm down to ∼20 nm, ultrascaled FETs were found to be contact limited. To reduce the contact resistance, monolayer tungsten oxyselenide (WOxSey) obtained using self-limiting oxidation of bilayer WSe2 was used as a p-type dopant. This led to ∼5× improvement in the ON-state performance and ∼9× reduction in the contact resistance. We were able to achieve a median ON-state current as high as ∼10 μA/μm for ultrascaled and doped p-type WSe2 FETs with Pd contacts. We also show the applicability of our monolayer doping strategy to other 2D materials such as MoS2, MoTe2, and MoSe2.

Temperature-Dependent Structural and Electrical Properties of Metal-Organic CVD MoS2 Films

Metal-Organic CVD method (MOCVD) allows for deposition of ultrathin 2D transition metal dichalcogenides (TMD) films of electronic quality onto wafer-scale substrates. In this work, the effect of temperature on structure, chemical states, and electronic qualities of the MOCVD MoS2 films were investigated. The results demonstrate that the temperature increase in the range of 650 °C to 950 °C results in non-monotonic average crystallite size variation. Atomic force microscopy (AFM), transmission electron microscopy (TEM), and Raman spectroscopy investigation has established the film crystal structure improvement with temperature increase in this range. At the same time, X-Ray photoelectron spectroscopy (XPS) method allowed to reveal non-stoichiometric phase fraction increase, corresponding to increased sulfur vacancies (VS) concentration from approximately 0.9 at.% to 3.6 at.%. Established dependency between the crystallite domains size and VS concentration suggests that these vacancies are form predominantly at the grain boundaries. The results suggest that an increased Vs concentration and enhanced charge carriers scattering at the grains' boundaries should be the primary reasons of films' resistivity increase from 4 kΩ·cm to 39 kΩ·cm.

Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T-4R structure for high-density memory

Emerging data-intensive computation has driven the advanced packaging and vertical stacking of integrated circuits, for minimized latency and energy consumption. Yet a monolithic three-dimensional (3D) integrated structure with interleaved logic and high-density memory layers has been difficult to achieve due to challenges in managing the thermal budget. Here we experimentally demonstrate a monolithic 3D integration of atomically-thin molybdenum disulfide (MoS2) transistors and 3D vertical resistive random-access memories (VRRAMs), with the MoS2 transistors stacked between the bottom-plane and top-plane VRRAMs. The whole fabrication process is integration-friendly (below 300 °C), and the measurement results confirm that the top-plane fabrication does not affect the bottom-plane devices. The MoS2 transistor can drive each layer of VRRAM into four resistance states. Circuit-level modeling of the monolithic 3D structure demonstrates smaller area, faster data transfer, and lower energy consumption than a planar memory. Such platform holds a high potential for energy-efficient 3D on-chip memory systems.

Two-Terminal MoS2 Memristor and the Homogeneous Integration with a MoS2 Transistor for Neural Networks

Memristors are promising candidates for constructing neural networks. However, their dissimilar working mechanism to that of the addressing transistors can result in a scaling mismatch, which may hinder efficient integration. Here, we demonstrate two-terminal MoS₂ memristors that work with a charge-based mechanism similar to that in transistors, which enables the homogeneous integration with MoS₂ transistors to realize one-transistor-one-memristor addressable cells for assembling programmable networks. The homogenously integrated cells are implemented in a 2 × 2 network array to demonstrate the enabled addressability and programmability. The potential for assembling a scalable network is evaluated in a simulated neural network using obtained realistic device parameters, which achieves over 91% pattern recognition accuracy. This study also reveals a generic mechanism and strategy that can be applied to other semiconducting devices for the engineering and homogeneous integration of memristive systems.

Hardware and Information Security Primitives Based on 2D Materials and Devices

Hardware security is a major concern for the entire semiconductor ecosystem that accounts for billions of dollars in annual losses. Similarly, information security is a critical need for the rapidly proliferating edge devices that continuously collect and communicate a massive volume of data. While silicon-based complementary metal-oxide-semiconductor technology offers security solutions, these are largely inadequate, inefficient, and often inconclusive, as well as resource intensive in time, energy, and cost, leading to tremendous room for innovation in this field. Furthermore, silicon-based security primitives have shown vulnerability to machine learning (ML) attacks. In recent years, 2D materials such as graphene and transition metal dichalcogenides have been intensely explored to mitigate these security challenges. In this review, 2D-materials-based hardware security solutions such as camouflaging, true random number generation, watermarking, anticounterfeiting, physically unclonable functions, and logic locking of integrated circuits (ICs) are summarized with accompanying discussion on their reliability and resilience to ML attacks. In addition, the role of native defects in 2D materials in developing high entropy hardware security primitives is also examined. Finally, the existing challenges for 2D materials, which must be overcome for large-scale deployment of 2D ICs to meet the security needs of the semiconductor industry, are discussed.

Ultrascaled Contacts to Monolayer MoS2 Field Effect Transistors

Two-dimensional (2D) semiconductors possess promise for the development of field-effect transistors (FETs) at the ultimate scaling limit due to their strong gate electrostatics. However, proper FET scaling requires reduction of both channel length (L_CH) and contact length (L_C), the latter of which has remained a challenge due to increased current crowding at the nanoscale. Here, we investigate Au contacts to monolayer MoS₂ FETs with L_CH down to 100 nm and L_C down to 20 nm to evaluate the impact of contact scaling on FET performance. Au contacts are found to display a ∼2.5× reduction in the ON-current, from 519 to 206 μA/μm, when L_C is scaled from 300 to 20 nm. It is our belief that this study is warranted to ensure an accurate representation of contact effects at and beyond the technology nodes currently occupied by silicon.

Ballistic two-dimensional InSe transistors

The International Roadmap for Devices and Systems (IRDS) forecasts that, for silicon-based metal-oxide-semiconductor (MOS) field-effect transistors (FETs), the scaling of the gate length will stop at 12 nm and the ultimate supply voltage will not decrease to less than 0.6 V (ref. 1). This defines the final integration density and power consumption at the end of the scaling process for silicon-based chips. In recent years, two-dimensional (2D) layered semiconductors with atom-scale thicknesses have been explored as potential channel materials to support further miniaturization and integrated electronics. However, so far, no 2D semiconductor-based FETs have exhibited performances that can surpass state-of-the-art silicon FETs. Here we report a FET with 2D indium selenide (InSe) with high thermal velocity as channel material that operates at 0.5 V and achieves record high transconductance of 6 mS μm-1 and a room-temperature ballistic ratio in the saturation region of 83%, surpassing those of any reported silicon FETs. An yttrium-doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. Our InSe FETs can effectively suppress short-channel effects with a low subthreshold swing (SS) of 75 mV per decade and drain-induced barrier lowering (DIBL) of 22 mV V-1. Furthermore, low contact resistance of 62 Ω μm is reliably extracted in 10-nm ballistic InSe FETs, leading to a smaller intrinsic delay and much lower energy-delay product (EDP) than the predicted silicon limit.

Effects of Channel Length Scaling on the Electrical Characteristics of Multilayer MoS2 Field Effect Transistor

With the rapid miniaturization of integrated chips in recent decades, aggressive geometric scaling of transistor dimensions to nanometric scales has become imperative. Recent works have reported the usefulness of 2D transition metal dichalcogenides (TMDs) like MoS₂ in MOSFET fabrication due to their enhanced active surface area, thin body, and non-zero bandgap. However, a systematic study on the effects of geometric scaling down to sub-10-nm nodes on the performance of MoS₂ MOSFETs is lacking. Here, the authors present an extensive study on the performance of MoS₂ FETs when geometrically scaled down to the sub-10 nm range. Transport properties are modelled using drift-diffusion equations in the classical regime and self-consistent Schrödinger-Poisson solution using NEGF formulation in the quantum regime. By employing the device modeling tool COMSOL for the classical regime, drain current vs. gate voltage (I_D vs. V_GS) plots were simulated. On the other hand, NEGF formulation for quantum regions is performed using MATLAB, and transfer characteristics are obtained. The effects of scaling device dimensions, such as channel length and contact length, are evaluated based on transfer characteristics by computing performance metrics like drain-induced barrier lowering (DIBL), on-off currents, subthreshold swing, and threshold voltage.

Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS2-Channel at Sub-2 nm Technology Node

In this work, WS2 was adopted as a channel material among transition metal dichalcogenides (TMD) materials that have recently been in the spotlight, and the circuit power performance (power consumption, operating frequency) of the monolayer WS2 field-effect transistor with a double gate structure (DG WS2-FET) was analyzed. It was confirmed that the effective capacitance, which is circuit power performance, was greatly changed by the extrinsic capacitance components of DG WS2-FET, and the spacer region length (LSPC) and dielectric constant (KSPC) values of the spacer that could affect the extrinsic capacitance components were analyzed to identify the circuit power performance. As a result, when LSPC is increased by 1.5 nm with the typical spacer material (KSPC = 7.5), increased operating speed (+4.9%) and reduced active power (–6.8%) are expected. In addition, it is expected that the spacer material improvement by developing the low-k spacer from KSPC = 7.5 to KSPC = 2 at typical LSPC = 8 nm can increase the operating speed by 36.8% while maintaining similar active power consumption. Considering back-end-of-line (BEOL), the change in circuit power performance according to wire length was also analyzed. From these results, it can be seen that reducing the capacitance components of the extrinsic region is very important for improving the circuit power performance of the DG WS2-FET.

Engineering van der Waals Materials for Advanced Metaphotonics

The outstanding chemical and physical properties of 2D materials, together with their atomically thin nature, make them ideal candidates for metaphotonic device integration and construction, which requires deep subwavelength light-matter interaction to achieve optical functionalities beyond conventional optical phenomena observed in naturally available materials. In addition to their intrinsic properties, the possibility to further manipulate the properties of 2D materials via chemical or physical engineering dramatically enhances their capability, evoking new science on light-matter interaction, leading to leaped performance of existing functional devices and giving birth to new metaphotonic devices that were unattainable previously. Comprehensive understanding of the intrinsic properties of 2D materials, approaches and capabilities for chemical and physical engineering methods, the resulting property modifications and novel functionalities, and applications of metaphotonic devices are provided in this review. Through reviewing the detailed progress in each aspect and the state-of-the-art achievement, insightful analyses of the outstanding challenges and future directions are elucidated in this cross-disciplinary comprehensive review with the aim to provide an overall development picture in the field of 2D material metaphotonics and promote rapid progress in this fast emerging and prosperous field.

Fermi Level Pinning Dependent 2D Semiconductor Devices: Challenges and Prospects

Motivated by the high expectation for efficient electrostatic modulation of charge transport at very low voltages, atomically thin 2D materials with a range of bandgaps are investigated extensively for use in future semiconductor devices. However, researchers face formidable challenges in 2D device processing mainly originated from the out-of-plane van der Waals (vdW) structure of ultrathin 2D materials. As major challenges, untunable Schottky barrier height and the corresponding strong Fermi level pinning (FLP) at metal interfaces are observed unexpectedly with 2D vdW materials, giving rise to unmodulated semiconductor polarity, high contact resistance, and lowered device mobility. Here, FLP observed from recently developed 2D semiconductor devices is addressed differently from those observed from conventional semiconductor devices. It is understood that the observed FLP is attributed to inefficient doping into 2D materials, vdW gap present at the metal interface, and hybridized compounds formed under contacting metals. To provide readers with practical guidelines for the design of 2D devices, the impact of FLP occurring in 2D semiconductor devices is further reviewed by exploring various origins responsible for the FLP, effects of FLP on 2D device performances, and methods for improving metallic contact to 2D materials.

Enhancement of InSe Field-Effect-Transistor Performance against Degradation of InSe Film in Air Environment

The degradation of InSe film and its impact on field effect transistors are investigated. After the exposure to atmospheric environment, 2D InSe flakes produce irreversible degradation that cannot be stopped by the passivation layer of h-BN, causing a rapid decrease for InSe FETs performance, which is attributed to the large number of traps formed by the oxidation of 2D InSe and adsorption to impurities. The residual photoresist in lithography can cause unwanted doping to the material and reduce the performance of the device. To avoid contamination, a high-performance InSe FET is achieved by a using hard shadow mask instead of the lithography process. The high-quality channel surface is manifested by the hysteresis of the transfer characteristic curve. The hysteresis of InSe FET is less than 0.1 V at V_d of 0.2, 0.5, and 1 V. And a high on/off ratio of 1.25 × 10⁸ is achieved, as well relative high I_on of 1.98 × 10⁻⁴ A and low SS of 70.4 mV/dec at V_d = 1 V are obtained, demonstrating the potential for InSe high-performance logic device.