Single-nanostructure bandgap engineering enabled by magnetic-pulling thermal evaporation growth

Realizing the substantial potential of bottom-up 1D semiconductor nanostructures in developing functional nanodevices calls for dedicated single-nanostructure bandgap engineering by various growth approaches. Although thermal evaporation has been advised as a facile approach for most semiconductors to form 1D nanostructures from bottom-up, its capability of achieving single-nanostructure bandgap engineering was considered a challenge. In 2011, we succeeded in the direct growth of composition-graded CdS1-x Se x (0 ≤ x ≤ 1) nanowires by upgrading the thermal-evaporation tube furnace with a home-made magnetic-pulling module. This report aims to provide a comprehensive review of the latest advances in the single-nanostructure bandgap engineering enabled by the magnetic-pulling thermal evaporation growth. The report begins with the description of different magnetic-pulling thermal evaporation strategies associated with diverse examples of composition-engineered 1D nanostructures. Following is an elaboration on their optoelectronic applications based on the resulting single-nanostructure bandgap engineering, including monolithic white-light sources, proof-of-concept asymmetric light propagation and wavelength splitters, monolithic multi-color and white-light lasers, broadband-response photodetectors, high-performance transistors, and recently the most exciting single-nanowire spectrometer. In the end, this report concludes with some personal perspectives on the directions toward which future research might be advanced.

Erasable memory properties of spectral selectivity modulated by temperature and bias in an individual CdS nanobelt-based photodetector

Single CdS nanobelt-based photodetectors are strongly dependent on bias and temperature. They not only show a strong photoresponse to close bandgap energy light with ultrahigh responsivity of approximately 10⁷ A W^-1, large photo-to-dark current ratio of 10⁴, photoconductive gain of 10⁷, and fast response and recovery speed at a large bias of 20 V, but can also show a weak photoresponse to above- and below-bandgap energy light. Moreover, their spectral response range can show tunable selectivity to above- and below-bandgap light, which can be accurately controlled by temperature and bias. More importantly, the modulated spectral response characteristics show excellent memory behaviour after reversible writing and erasing by using temperature and bias. In nanostructures, abundant surface states and stacking fault-related traps play a vital role in the ultrahigh photoresponse to bandgap light and the erasable memory effect on spectral response range selectivity. Given the erasable memory of the spectral response selectivity with excellent photoconduction performance, the CdS NBs possess important applications in new-generation photodetection and photomemory devices.

In2O3 Nanowire Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and Their Logic Applications

Heat dissipation is a key issue for scaling metal-oxide-semiconductor field-effect transistors (MOSFETs). The Boltzmann distribution of electrons imposes a physical limit on the subthreshold swing (SS), which impedes both the reduction of the switching energy and the further increase of the device density. The negative capacitance effect is proposed to rescue MOSFETs from this phenomenon called "Boltzmann tyranny". Herein, we report In₂O₃ nanowire (NW) transistors with SS values in the sub-60 mV/dec region, which utilize the ferroelectric P(VDF-TrFE) as the dielectric layer. An ultralow SS down to ∼10 mV/dec is observed and spans over 5 orders of magnitude in the drain current. Meanwhile, a high on/off ratio of more than 10⁸ and a transconductance ( g_m) of 2.3 μS are obtained simultaneously at V_d = 0.1 V. The results can be understood by the "voltage amplification" effect induced from the negative capacitance effect. Moreover, the steep slope FET-based inverters indicate a high voltage gain of 41.6. In addition to the NOR and NAND gates, the Schmitt trigger inverters containing only one steep slope FET are demonstrated. This work demonstrates an avenue for low-power circuit design with a steep SS.

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls

Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm²) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10⁸, 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

One-dimensional CdS nanostructures: synthesis, properties, and applications

One-dimensional (1D) semiconductor nanostructures are of prime interest due to their potential in investigating the size and dimensionality dependence of the materials' physical properties and constructing nanoscale electronic and optoelectronic devices. Cadmium sulfide (CdS) is an important semiconductor compound of the II-VI group, and its synthesis and properties have been of growing interest owing to prominent applications in several fields. This article provides a comprehensive review of the state-of-the-art research activities that focus on the rational synthesis, novel properties and unique applications of 1D CdS nanostructures in nanotechnology. It begins with the rational design and synthesis of 1D CdS nanostructures, and then highlights a range of unique properties and applications (e.g. photoluminescence, cathodoluminescence, electrochemiluminescence, photocatalysis, lasers, waveguides, modulators, solar cells, field-effect transistors, photodetectors, field-emitters, and nanogenerators) associated with them. Finally, the review is concluded with the author outlook of the perspectives with respect to future research on 1D CdS nanostructures.

Ultrahigh-performance inverters based on CdS nanobelts

We report ultrahigh-performance inverters, each consisting of two top-gate metal-oxide-semiconductor field-effect transistors based on n-CdS nanobelts. High-kappa HfO(2) dielectrics are used as the top-gate oxide layers. The inverters have a large supply voltage (V(DD)) range (from 50 mV to 10 V) and very high voltage gain ( approximately 10, 100, and 1000 at V(DD) = 0.2, 1, and 10 V, respectively). Current consumption is less than 7 nA at V(DD) = 1 V, corresponding to a power consumption of less than 7 nW. The high and low output voltages are close to full rail. The inverters also exhibit good dynamic behavior with square wave input at frequencies up to 1 kHz. The operation of the inverters is analyzed in detail. The inverters are promising for future low power high performance logic circuit applications.