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Lee S, Huang Y, Chang YF, Baik S, Lee JC, Koo M. Enhancing simulation feasibility for multi-layer 2D MoS 2 RRAM devices: reliability performance learnings from a passive network model. Phys Chem Chem Phys 2024; 26:20962-20970. [PMID: 39046422 DOI: 10.1039/d4cp02669a] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Journal Information] [Subscribe] [Scholar Register] [Indexed: 07/25/2024]
Abstract
While two-dimensional (2D) MoS2 has recently shown promise as a material for resistive random-access memory (RRAM) devices due to its demonstrated resistive switching (RS) characteristics, its practical application faces a significant challenge in industry regarding its limited yield and endurance. Our earlier work introduced an effective switching layer model to understand RS behavior in both mono- and multi-layered MoS2. However, functioning as a phenomenological percolation modeling tool, it lacks the capability to accurately simulate the intricate current-voltage (I-V) characteristics of the device, thereby hindering its practical applicability in 2D RRAM research. In contrast to the established conductive filament model for oxide-based RRAM, the RS mechanism in 2D RRAM remains elusive. This paper presents a novel simulator aimed at providing an intuitive, visual representation of the stochastic behaviors involved in the RS process of multi-layer 2D MoS2 RRAM devices. Building upon the previously proposed phenomenological simulator for 2D RRAM, users can now simulate both the I-V characteristics and the resistive switching behaviors of the RRAM devices. Through comparison with experimental data, it was observed that yield and endurance characteristics are linked to defect distributions in MoS2.
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Affiliation(s)
- Seonjeong Lee
- School of Electrical and Computer Engineering, University of Seoul, Seoul 02504, South Korea
| | - Yifu Huang
- Department of Electrical and Computer Engineering, University of Texas at Austin, 10100 Burnet Road, 78758 Austin, TX, USA
| | - Yao-Feng Chang
- Intel Corporation, 2501 NE Century Road, 97124 Hillsboro, OR, USA
| | - Seungjae Baik
- Semiconductor Research and Development Center, Samsung Electronics, Hwaseong-si 18448, South Korea
| | - Jack C Lee
- Department of Electrical and Computer Engineering, University of Texas at Austin, 10100 Burnet Road, 78758 Austin, TX, USA
| | - Minsuk Koo
- Department of Computer Science and Engineering, Incheon National University, Incheon 22012, South Korea.
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Garlapati SK, Simanjuntak FM, Stathopoulos S, A SJ, Napari M, Prodromakis T. Compliance-free, analog RRAM devices based on SnO x. Sci Rep 2024; 14:14163. [PMID: 38898073 PMCID: PMC11187170 DOI: 10.1038/s41598-024-64662-9] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Key Words] [Grants] [Track Full Text] [Journal Information] [Subscribe] [Scholar Register] [Received: 03/28/2023] [Accepted: 06/11/2024] [Indexed: 06/21/2024] Open
Abstract
Brain-inspired resistive random-access memory (RRAM) technology is anticipated to outperform conventional flash memory technology due to its performance, high aerial density, low power consumption, and cost. For RRAM devices, metal oxides are exceedingly investigated as resistive switching (RS) materials. Among different oxides, tin oxide (SnOx) received minimal attention, although it possesses excellent electronic properties. Herein, we demonstrate compliance-free, analog resistive switching behavior with several stable states in Ti/Pt/SnOx/Pt RRAM devices. The compliance-free nature might be due to the high internal resistance of SnOx films. The resistance of the films was modulated by varying Ar/O2 ratio during the sputtering process. The I-V characteristics revealed a well-expressed high resistance state (HRS) and low resistance states (LRS) with bipolar memristive switching mechanism. By varying the pulse amplitude and width, different resistance states have been achieved, indicating the analog switching characteristics of the device. Furthermore, the devices show excellent retention for eleven states over 1000 s with an endurance of > 100 cycles.
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Affiliation(s)
- Suresh Kumar Garlapati
- Department of Materials Science and Metallurgical Engineering, Indian Institute of Technology Hyderabad, Hyderabad, 502285, India.
| | | | - Spyros Stathopoulos
- Centre for Electronics Frontiers, School of Engineering, University of Edinburgh, Edinburgh, UK
| | - Syed Jalaluddeen A
- Department of Materials Science and Metallurgical Engineering, Indian Institute of Technology Hyderabad, Hyderabad, 502285, India
| | - Mari Napari
- Department of Physics, King's College London, London, WC2R 2LS, UK
| | - Themis Prodromakis
- Centre for Electronics Frontiers, School of Engineering, University of Edinburgh, Edinburgh, UK.
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R RT, Das RR, Reghuvaran C, James A. Graphene-based RRAM devices for neural computing. Front Neurosci 2023; 17:1253075. [PMID: 37886675 PMCID: PMC10598392 DOI: 10.3389/fnins.2023.1253075] [Citation(s) in RCA: 1] [Impact Index Per Article: 1.0] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 07/04/2023] [Accepted: 09/13/2023] [Indexed: 10/28/2023] Open
Abstract
Resistive random access memory is very well known for its potential application in in-memory and neural computing. However, they often have different types of device-to-device and cycle-to-cycle variability. This makes it harder to build highly accurate crossbar arrays. Traditional RRAM designs make use of various filament-based oxide materials for creating a channel that is sandwiched between two electrodes to form a two-terminal structure. They are often subjected to mechanical and electrical stress over repeated read-and-write cycles. The behavior of these devices often varies in practice across wafer arrays over these stresses when fabricated. The use of emerging 2D materials is explored to improve electrical endurance, long retention time, high switching speed, and fewer power losses. This study provides an in-depth exploration of neuro-memristive computing and its potential applications, focusing specifically on the utilization of graphene and 2D materials in RRAM for neural computing. The study presents a comprehensive analysis of the structural and design aspects of graphene-based RRAM, along with a thorough examination of commercially available RRAM models and their fabrication techniques. Furthermore, the study investigates the diverse range of applications that can benefit from graphene-based RRAM devices.
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Affiliation(s)
| | | | | | - Alex James
- Digital University, Thiruvananthapuram, Kerala, India
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Yon V, Amirsoleimani A, Alibart F, Melko RG, Drouin D, Beilliard Y. Exploiting Non-idealities of Resistive Switching Memories for Efficient Machine Learning. FRONTIERS IN ELECTRONICS 2022. [DOI: 10.3389/felec.2022.825077] [Citation(s) in RCA: 1] [Impact Index Per Article: 0.5] [Reference Citation Analysis] [Abstract] [Track Full Text] [Journal Information] [Subscribe] [Scholar Register] [Indexed: 11/13/2022] Open
Abstract
Novel computing architectures based on resistive switching memories (also known as memristors or RRAMs) have been shown to be promising approaches for tackling the energy inefficiency of deep learning and spiking neural networks. However, resistive switch technology is immature and suffers from numerous imperfections, which are often considered limitations on implementations of artificial neural networks. Nevertheless, a reasonable amount of variability can be harnessed to implement efficient probabilistic or approximate computing. This approach turns out to improve robustness, decrease overfitting and reduce energy consumption for specific applications, such as Bayesian and spiking neural networks. Thus, certain non-idealities could become opportunities if we adapt machine learning methods to the intrinsic characteristics of resistive switching memories. In this short review, we introduce some key considerations for circuit design and the most common non-idealities. We illustrate the possible benefits of stochasticity and compression with examples of well-established software methods. We then present an overview of recent neural network implementations that exploit the imperfections of resistive switching memory, and discuss the potential and limitations of these approaches.
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Abstract
Personal, portable, and wearable electronics have become items of extensive use in daily life. Their fabrication requires flexible electronic components with high storage capability or with continuous power supplies (such as solar cells). In addition, formerly rigid tools such as electrochromic windows find new utilizations if they are fabricated with flexible characteristics. Flexibility and performances are determined by the material composition and fabrication procedures. In this regard, low-cost, easy-to-handle materials and processes are an asset in the overall production processes and items fruition. In the present mini-review, the most recent approaches are described in the production of flexible electronic devices based on NiO as low-cost material enhancing the overall performances. In particular, flexible NiO-based all-solid-state supercapacitors, electrodes electrochromic devices, temperature devices, and ReRAM are discussed, thus showing the potential of NiO as material for future developments in opto-electronic devices.
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Zahoor F, Azni Zulkifli TZ, Khanday FA. Resistive Random Access Memory (RRAM): an Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (mlc) Storage, Modeling, and Applications. NANOSCALE RESEARCH LETTERS 2020; 15:90. [PMID: 32323059 PMCID: PMC7176808 DOI: 10.1186/s11671-020-03299-9] [Citation(s) in RCA: 99] [Impact Index Per Article: 24.8] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Received: 09/19/2019] [Accepted: 03/17/2020] [Indexed: 05/10/2023]
Abstract
In this manuscript, recent progress in the area of resistive random access memory (RRAM) technology which is considered one of the most standout emerging memory technologies owing to its high speed, low cost, enhanced storage density, potential applications in various fields, and excellent scalability is comprehensively reviewed. First, a brief overview of the field of emerging memory technologies is provided. The material properties, resistance switching mechanism, and electrical characteristics of RRAM are discussed. Also, various issues such as endurance, retention, uniformity, and the effect of operating temperature and random telegraph noise (RTN) are elaborated. A discussion on multilevel cell (MLC) storage capability of RRAM, which is attractive for achieving increased storage density and low cost is presented. Different operation schemes to achieve reliable MLC operation along with their physical mechanisms have been provided. In addition, an elaborate description of switching methodologies and current voltage relationships for various popular RRAM models is covered in this work. The prospective applications of RRAM to various fields such as security, neuromorphic computing, and non-volatile logic systems are addressed briefly. The present review article concludes with the discussion on the challenges and future prospects of the RRAM.
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Affiliation(s)
- Furqan Zahoor
- Department of Electrical and Electronics Engineering, Universiti Teknologi Petronas, Seri Iskandar, Perak, 32610 Malaysia
| | - Tun Zainal Azni Zulkifli
- Department of Electrical and Electronics Engineering, Universiti Teknologi Petronas, Seri Iskandar, Perak, 32610 Malaysia
| | - Farooq Ahmad Khanday
- P.G. Department of Electronics and Instrumentation Technology, University of Kashmir, Srinagar, Jammu and Kashmir, 190005 India
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Bhattacharjee S, Caruso E, McEvoy N, Ó Coileáin C, O'Neill K, Ansari L, Duesberg GS, Nagle R, Cherkaoui K, Gity F, Hurley PK. Insights into Multilevel Resistive Switching in Monolayer MoS 2. ACS APPLIED MATERIALS & INTERFACES 2020; 12:6022-6029. [PMID: 31920069 DOI: 10.1021/acsami.9b15677] [Citation(s) in RCA: 15] [Impact Index Per Article: 3.8] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 05/23/2023]
Abstract
The advent of two-dimensional materials has opened a plethora of opportunities in accessing ultrascaled device dimensions for future logic and memory applications. In this work, we demonstrate that a single layer of large-area chemical vapor deposition-grown molybdenum disulfide (MoS2) sandwiched between two metal electrodes can be tuned to show multilevel nonvolatile resistive memory states with resistance values separated by 5 orders of magnitude. The switching process is unipolar and thermochemically driven requiring significant Joule heating in the reset process. Temperature-dependent electrical measurements coupled with semiclassical charge transport models suggest that the transport in these devices varies significantly in the initial (pristine) state, high resistance state, and low resistance state. In the initial state, the transport is a one-step direct tunneling (at low voltage biases) and Fowler Nordeim tunneling (at higher bias) with an effective barrier height of 0.33 eV, which closely matches the Schottky barrier at the MoS2/Au interface. In the high resistive state, trap-assisted tunneling provides a reasonable fit to experimental data for a trap height of 0.82 eV. Density functional theory calculations suggest the possibility of single- and double-sulfur vacancies as the microscopic origins of these trap sites. The temperature-dependent behavior of the set and reset process are explained by invoking the probability of defect (sulfur vacancy) creation and mobility of sulfur ions. Finally, conductive atomic force microscopy measurements confirm that the multifilamentary resistive memory effects are inherent to a single-crystalline MoS2 triangle and not necessarily dependent on grain boundaries. The insights suggested in this work are envisioned to open up possibilities for ultrascaled, multistate, resistive memories for next-generation digital memory and neuromorphic applications.
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Affiliation(s)
| | - Enrico Caruso
- Tyndall National Institute , Cork T12 R5CP , Ireland
| | - Niall McEvoy
- AMBER & School of Chemistry , Trinity College Dublin , Dublin 2 , Ireland
| | - Cormac Ó Coileáin
- AMBER & School of Chemistry , Trinity College Dublin , Dublin 2 , Ireland
| | - Katie O'Neill
- AMBER & School of Chemistry , Trinity College Dublin , Dublin 2 , Ireland
| | - Lida Ansari
- Tyndall National Institute , Cork T12 R5CP , Ireland
| | | | - Roger Nagle
- Tyndall National Institute , Cork T12 R5CP , Ireland
| | | | - Farzan Gity
- Tyndall National Institute , Cork T12 R5CP , Ireland
| | - Paul K Hurley
- Tyndall National Institute , Cork T12 R5CP , Ireland
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Hsieh YL, Su WH, Huang CC, Su CY. Solution-processed black phosphorus nanoflakes for integrating nonvolatile resistive random access memory and the mechanism unveiled. NANOTECHNOLOGY 2019; 30:445702. [PMID: 31349243 DOI: 10.1088/1361-6528/ab3606] [Citation(s) in RCA: 1] [Impact Index Per Article: 0.2] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/10/2023]
Abstract
In this study, we demonstrated the integration of black phosphorus (BP) nanoflakes in a resistive random access memory (RRAM) with a facile and complementary metal-oxide-semiconductor-compatible process. The solution-processed BP nanoflakes embedded in polystyrene (PS) as an active layer were sandwiched between aluminum electrodes (Al/BP:PS/Al). The device shows a figure of merit with typical bipolar behavior and forming-free characteristics as well as excellent memory performances such as nonvolatile, low operation voltage (1.75 V) and high ON/OFF ratio (>102) as well as the long retention time (>1500 s). The improved device performances were attributed to the formation of effective trap sites from the hybrid structure of the active layer (BP:PS), especially the BP nanoflakes and the partly oxidized species (P x O y ). Moreover, the extrinsic aluminum oxide layer was observed after the device operation. The mechanism of switching behavior was further unveiled through the carrier transport models, which confirms the conductive mechanisms of space-charge-limited current and Ohmic conductance at high resistance state (HRS) and low resistance state, respectively. Additionally, in the high electric field at HRS, the transfer curve was well fitted with the Poole-Frenkel emission model, which could be attributed to the formation of the aluminum oxide layer. Accordingly, both the trapping/de-trapping of carriers and the formation/rupture of conductive filaments were introduced as transport mechanisms in our devices. Although the partial P x O y species on BP were inevitable during the liquid phase exfoliation process, which was regarded as the disadvantages for various applications, it turns to a key point for improving performances in memory devices. The proposed approach to integrating BP nanoflakes in the active layer of the RRAM device could pave the way for next-generation memory devices.
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Affiliation(s)
- Yu-Ling Hsieh
- Dep. of Mechanical Engineering, National Central University, Tao-Yuan 32001, Taiwan
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9
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Shen Z, Qi Y, Mitrovic IZ, Zhao C, Hall S, Yang L, Luo T, Huang Y, Zhao C. Effect of Annealing Temperature for Ni/AlO x/Pt RRAM Devices Fabricated with Solution-Based Dielectric. MICROMACHINES 2019; 10:mi10070446. [PMID: 31269730 PMCID: PMC6680579 DOI: 10.3390/mi10070446] [Citation(s) in RCA: 21] [Impact Index Per Article: 4.2] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Download PDF] [Figures] [Subscribe] [Scholar Register] [Received: 01/01/1970] [Revised: 06/25/2019] [Accepted: 06/28/2019] [Indexed: 11/19/2022]
Abstract
Resistive random access memory (RRAM) devices with Ni/AlOx/Pt-structure were manufactured by deposition of a solution-based aluminum oxide (AlOx) dielectric layer which was subsequently annealed at temperatures from 200 °C to 300 °C, in increments of 25 °C. The devices displayed typical bipolar resistive switching characteristics. Investigations were carried out on the effect of different annealing temperatures for associated RRAM devices to show that performance was correlated with changes of hydroxyl group concentration in the AlOx thin films. The annealing temperature of 250 °C was found to be optimal for the dielectric layer, exhibiting superior performance of the RRAM devices with the lowest operation voltage (<1.5 V), the highest ON/OFF ratio (>104), the narrowest resistance distribution, the longest retention time (>104 s) and the most endurance cycles (>150).
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Affiliation(s)
- Zongjie Shen
- Department of Electrical and Electronic Engineering, Xi'an Jiaotong-Liverpool University, Suzhou 215123, China
- Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3BX, UK
| | - Yanfei Qi
- Department of Electrical and Electronic Engineering, Xi'an Jiaotong-Liverpool University, Suzhou 215123, China
- School of Electronic and Information Engineering, Xi'an Jiaotong University, Xi'an 710061, China
| | - Ivona Z Mitrovic
- Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3BX, UK
| | - Cezhou Zhao
- Department of Electrical and Electronic Engineering, Xi'an Jiaotong-Liverpool University, Suzhou 215123, China
- Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3BX, UK
| | - Steve Hall
- Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3BX, UK
| | - Li Yang
- Department of Chemistry, Xi'an Jiaotong-Liverpool University, Suzhou 215123, China
- Department of Chemistry, University of Liverpool, Liverpool L69 3BX, UK
| | - Tian Luo
- Department of Electrical and Electronic Engineering, Xi'an Jiaotong-Liverpool University, Suzhou 215123, China
- Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3BX, UK
| | - Yanbo Huang
- Department of Electrical and Electronic Engineering, Xi'an Jiaotong-Liverpool University, Suzhou 215123, China
- Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3BX, UK
| | - Chun Zhao
- Department of Electrical and Electronic Engineering, Xi'an Jiaotong-Liverpool University, Suzhou 215123, China.
- Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3BX, UK.
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Kim S, Chen J, Chen YC, Kim MH, Kim H, Kwon MW, Hwang S, Ismail M, Li Y, Miao XS, Chang YF, Park BG. Neuronal dynamics in HfO x/AlO y-based homeothermic synaptic memristors with low-power and homogeneous resistive switching. NANOSCALE 2018; 11:237-245. [PMID: 30534752 DOI: 10.1039/c8nr06694a] [Citation(s) in RCA: 19] [Impact Index Per Article: 3.2] [Reference Citation Analysis] [Abstract] [MESH Headings] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/09/2023]
Abstract
We studied the pseudo-homeothermic synaptic behaviors by integrating complimentary metal-oxide-semiconductor-compatible materials (hafnium oxide, aluminum oxide, and silicon substrate). A wide range of temperatures, from 25 °C up to 145 °C, in neuronal dynamics was achieved owing to the homeothermic properties and the possibility of spike-induced synaptic behaviors was demonstrated, both presenting critical milestones for the use of emerging memristor-type neuromorphic computing systems in the near future. Biological synaptic behaviors, such as long-term potentiation, long-term depression, and spike-timing-dependent plasticity, are developed systematically, and comprehensive neural network analysis is used for temperature changes and to conform spike-induced neuronal dynamics, providing a new research regime of neurocomputing for potentially harsh environments to overcome the self-heating issue in neuromorphic chips.
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Affiliation(s)
- Sungjun Kim
- School of Electronics Engineering, Chungbuk National University, Cheongju 28644, South Korea
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Chen YC, Hu ST, Lin CY, Fowler B, Huang HC, Lin CC, Kim S, Chang YF, Lee JC. Graphite-based selectorless RRAM: improvable intrinsic nonlinearity for array applications. NANOSCALE 2018; 10:15608-15614. [PMID: 30090909 DOI: 10.1039/c8nr04766a] [Citation(s) in RCA: 6] [Impact Index Per Article: 1.0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/08/2023]
Abstract
Selectorless graphite-based resistive random-access memory (RRAM) has been demonstrated by utilizing the intrinsic nonlinear resistive switching (RS) characteristics, without an additional selector or transistor for low-power RRAM array application. The low effective dielectric constant value (k) layer of graphite or graphite oxide is utilized, which is beneficial in suppressing sneak-path currents in the crossbar RRAM array. The tail-bits with low nonlinearity can be manipulated by the positive voltage pulse, which in turn can alleviate variability and reliability issues. Our results provide additional insights for built-in nonlinearity in 1R-only selectorless RRAMs, which are applicable to the low-power memory array, ultrahigh density storage, and in-memory neuromorphic computational configurations.
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Affiliation(s)
- Ying-Chen Chen
- Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78758, USA.
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Ávila-Niño JA, Reyes-Reyes M, López-Sandoval R. Study of the presence of spherical deformations on the Al top electrode due to electroforming in rewritable organic resistive memories. Phys Chem Chem Phys 2017; 19:25691-25696. [PMID: 28906515 DOI: 10.1039/c7cp04975g] [Citation(s) in RCA: 3] [Impact Index Per Article: 0.4] [Reference Citation Analysis] [Abstract] [Track Full Text] [Journal Information] [Subscribe] [Scholar Register] [Indexed: 11/21/2022]
Abstract
Physical deformations are observed at the top electrodes during the electroforming process in Al/PEDOT:PSS + nitrogen doped multiwalled carbon nanotube (N-MWCNTs)/Al rewritable resistive memory devices. These physical deformations arise from electrochemical reactions, i.e., a reduction reaction in the native Al oxide layer, which are similar to those reported in TiO2-based resistive memory devices. These memory devices are electroformed at the ON state using an ∼-2 V pulse or at the OFF state using an ∼3 V pulse. These processes are current-controlled; a minimum compliance current is necessary to obtain the electroforming of the device, generally between 5 to 10 mA. SEM and AFM micrographs show the presence of spherical deformations at the top electrode due to O2 gas formation generated by the reduction in the native AlOx layer during the electroformation, with a diameter of ∼7 micrometres for positive voltage or a smaller diameter of ∼3 micrometres for negative voltage. After top-electrode delamination, circular craters are found in the active layer in the vicinity of the N-MWCNTs, which only occurs when a negative voltage is used in the electroformation, indicating that film damage is induced by oxygen bubbles created at the bottom electrode/polymeric film interface.
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Affiliation(s)
- J A Ávila-Niño
- Advanced Materials Department, IPICYT, Camino a la Presa San José 2055, Col. Lomas 4a sección, San Luis Potosí 78216, Mexico.
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Kim S, Chang YF, Park BG. Understanding rectifying and nonlinear bipolar resistive switching characteristics in Ni/SiNx/p-Si memory devices. RSC Adv 2017. [DOI: 10.1039/c6ra28477a] [Citation(s) in RCA: 42] [Impact Index Per Article: 6.0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Journal Information] [Subscribe] [Scholar Register] [Indexed: 11/21/2022] Open
Abstract
Two resistive memory devices were prepared with different doping concentrations in the silicon bottom electrodes to explore the self-rectifying and nonlinear resistive switching characteristics of Ni/SiNx/p-Si devices.
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Affiliation(s)
- Sungjun Kim
- Department of Electrical and Computer Engineering
- Inter-University Semiconductor Research Center (ISRC)
- Seoul National University
- Seoul 08826
- South Korea
| | - Yao-Feng Chang
- Microelectronics Research Center
- The University of Texas at Austin
- Austin
- USA
| | - Byung-Gook Park
- Department of Electrical and Computer Engineering
- Inter-University Semiconductor Research Center (ISRC)
- Seoul National University
- Seoul 08826
- South Korea
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