All-solution-processed nonvolatile flexible nano-floating gate memory devices

Contribution of Polymers to Electronic Memory Devices and Applications

Electronic memory devices, such as memristors, charge trap memory, and floating-gate memory, have been developed over the last decade. The use of polymers in electronic memory devices enables new opportunities, including easy-to-fabricate processes, mechanical flexibility, and neuromorphic applications. This review revisits recent efforts on polymer-based electronic memory developments. The versatile contributions of polymers for emerging memory devices are classified, providing a timely overview of such unconventional functionalities with a strong emphasis on the merits of polymer utilization. Furthermore, this review discusses the opportunities and challenges of polymer-based memory devices with respect to their device performance and stability for practical applications.

Recent Process of Flexible Transistor-Structured Memory

Flexible transistor-structured memory (FTSM) has attracted great attention for its important role in flexible electronics. For nonvolatile information storage, FTSMs with floating-gate, charge-trap, and ferroelectric mechanisms have been developed. By introducing an optical sensory module, FTSM can be operated by optical inputs to function as an optical memory transistor. As a special type of FTSM, transistor-structured artificial synapse emulates important functions of a biological synapse to mimic brain-inspired memory behaviors and nervous signal transmissions. This work reviews the recent development of the above mentioned FTSMs, with a focus on working mechanism and materials, and flexibility.

Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors

To investigate the behaviour of the organic memory transistors, graphene oxide (GO) was utilized as the floating gate in 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic memory transistors. A cross-linked, off-centre spin-coated and ozone-treated poly(methyl methacrylate) (cPMMA) was used as the insulating layer. High mobility and negligible hysteresis with very clear transistor behaviour were observed for the control transistors. On the other hand, memory transistors exhibited clear large hysteresis which is increased with increasing programming voltage. The shifts in the threshold voltage of the transfer characteristics as well as the hysteresis in the output characteristics were attributed to the charging and discharging of the floating gate. The counter-clockwise direction of hysteresis indicates that the process of charging and discharging the floating gate take place through the semiconductor/insulator interface. A clear shift in the threshold voltage was observed when different voltage pulses were applied to the gate. The non-volatile behaviour of the memory transistors was investigated in terms of charge retention. The memory transistors exhibited a large memory window (~30 V), and high charge density of (9.15 × 10¹¹ cm^-2).

Solution-Processed Nonvolatile Organic Transistor Memory Based on Semiconductor Blends

Solution-processed nonvolatile organic transistor memory devices are fabricated by employing semiconductor blends of p-channel 6,13-bis(triisopropylsilylethynyl)pentacene and n-channel poly{[ N, N'-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]- alt-5,5'-(2,2'-bithiophene)} (P(NDI2OD-2T); N2200) on polystyrene-brush as a polymer electret. Electret-based memory characteristics are significantly changed depending on the frontier molecular orbitals of the active semiconductors because the charge-trapping efficiency is mainly determined by the energy barrier to transfer electrons and holes from the active channel to the electret layer. A semiconductor mixture with an optimized blending ratio results in an efficient programming and erasing process. Thus, we obtained a remarkably high ratio of ON/OFF current (memory ratio) about 10⁷ and a large amount of shifts in the threshold voltage (memory window) between the programmed and erased states of 55 V, while single-component N2200 showed only writing-once-read-many (WORM)-type memory. Especially, the programmed data can be stably retained more than 10 years with a sufficient memory ratio of 10³. Furthermore, our semiconductor blend system leads to preferable vertical phase separation, which affords good reliability under a sequential memory operation condition as well as stability in ambient air. It is expected that our memory devices can be applied for versatile data storage in printed and flexible electronic applications.

Recent Advances of Flexible Data Storage Devices Based on Organic Nanoscaled Materials

Following the trend of miniaturization as per Moore's law, and facing the strong demand of next-generation electronic devices that should be highly portable, wearable, transplantable, and lightweight, growing endeavors have been made to develop novel flexible data storage devices possessing nonvolatile ability, high-density storage, high-switching speed, and reliable endurance properties. Nonvolatile organic data storage devices including memory devices on the basis of floating-gate, charge-trapping, and ferroelectric architectures, as well as organic resistive memory are believed to be favorable candidates for future data storage applications. In this Review, typical information on device structure, memory characteristics, device operation mechanisms, mechanical properties, challenges, and recent progress of the above categories of flexible data storage devices based on organic nanoscaled materials is summarized.

High-speed, solution-coatable memory based on Cu-SiO2 core-shell nanowires

Printable electronics has the potential to drastically reduce the environmental and economic costs associated with the production of electronic devices, as well as enable rapid prototyping of circuits and their printing on demand, similar to what 3D printing has done for structural objects. A major barrier to the realization of printable computers that can run programs is the lack of a solution-coatable non-volatile memory with performance metrics comparable to silicon-based devices. Here we demonstrate a non-volatile memory based on Cu-SiO₂ core-shell nanowires that can be printed from solution and exhibits on-off ratios of 10⁶, switching speeds of 50 ns, a low operating voltage of 2 V, and operates for at least 10⁴ cycles without failure. Each of these metrics is similar to or better than Flash memory (the write speed is 20 times faster than Flash). Memory architectures based on the individual memory cells demonstrated here could enable the printing of the more complex, embedded computing devices that are expected to make up an internet of things.

High Performance Transparent Transistor Memory Devices Using Nano-Floating Gate of Polymer/ZnO Nanocomposites

Nano-floating gate memory devices (NFGM) using metal nanoparticles (NPs) covered with an insulating polymer have been considered as a promising electronic device for the next-generation nonvolatile organic memory applications NPs. However, the transparency of the device with metal NPs is restricted to 60~70% due to the light absorption in the visible region caused by the surface plasmon resonance effects of metal NPs. To address this issue, we demonstrate a novel NFGM using the blends of hole-trapping poly (9-(4-vinylphenyl) carbazole) (PVPK) and electron-trapping ZnO NPs as the charge storage element. The memory devices exhibited a remarkably programmable memory window up to 60 V during the program/erase operations, which was attributed to the trapping/detrapping of charge carriers in ZnO NPs/PVPK composite. Furthermore, the devices showed the long-term retention time (>10(5) s) and WRER test (>200 cycles), indicating excellent electrical reliability and stability. Additionally, the fabricated transistor memory devices exhibited a relatively high transparency of 90% at the wavelength of 500 nm based on the spray-coated

PEDOT

PSS as electrode, suggesting high potential for transparent organic electronic memory devices.

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

A multifunctional polymer-graphene thin-film transistor with tunable transport regimes

Here we describe a strategy to fabricate multifunctional graphene-polymer hybrid thin-film transistors (PG-TFT) whose transport properties are tunable by varying the deposition conditions of liquid-phase exfoliated graphene (LPE-G) dispersions onto a dielectric surface and via thermal annealing post-treatments. In particular, the ionization energy (IE) of the LPE-G drop-cast on SiO2 can be finely adjusted prior to polymer deposition via thermal annealing in air environment, exhibiting values gradually changing from 4.8 eV up to 5.7 eV. Such a tunable graphene's IE determines dramatically different electronic interactions between the LPE-G and the semiconducting polymer (p- or n-type) sitting on its top, leading to devices where the output current of the PG-TFT can be operated from being completely turned off up to modulable. In fact upon increasing the surface coverage of graphene nanoflakes on the SiO2 the charge transport properties within the top polymer layer are modified from being semiconducting up to truly conductive (graphite-like). Significantly, when the IE of LPE-G is outside the polymer band gap, the PG-TFT can operate as a multifunctional three terminal switch (transistor) and/or memory device featuring high number of erase-write cycles. Our PG-TFT, based on a fine energy level engineering, represents a memory device operating without the need of a dielectric layer separating a floating gate from the active channel.

Design of an efficient charge-trapping layer with a built-in tunnel barrier for reliable organic-transistor memory

A fully feasible and versatile way to fabricate highly reliable organic-transistor memory devices is made possible by a novel design of the charge-trappling layer. Gold@silica (core-shell)-structured nanoparticles are synthesized and used as the charge-trapping layer. Superior electrical reliability is obtained because the silica shell acts as a built-in tunnel potential barrier.