1
|
Tano ZE, Cumpanas AD, Gorgen ARH, Rojhani A, Altamirano-Villarroel J, Landman J. Surgical Artificial Intelligence: Endourology. Urol Clin North Am 2024; 51:77-89. [PMID: 37945104 DOI: 10.1016/j.ucl.2023.06.004] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Key Words] [MESH Headings] [Track Full Text] [Journal Information] [Subscribe] [Scholar Register] [Indexed: 11/12/2023]
Abstract
Endourology is ripe with information that includes patient factors, laboratory tests, outcomes, and visual data, which is becoming increasingly complex to assess. Artificial intelligence (AI) has the potential to explore and define these relationships; however, humans might not be involved in the input, analysis, or even determining the methods of analysis. Herein, the authors present the current state of AI in endourology and highlight the need for urologists to share their proposed AI solutions for reproducibility outside of their institutions and prepare themselves to properly critique this new technology.
Collapse
Affiliation(s)
- Zachary E Tano
- Department of Urology, University of California, Irvine, 3800 West Chapman Avenue, Suite 7200, Orange, CA 92868, USA.
| | - Andrei D Cumpanas
- Department of Urology, University of California, Irvine, 3800 West Chapman Avenue, Suite 7200, Orange, CA 92868, USA
| | - Antonio R H Gorgen
- Department of Urology, University of California, Irvine, 3800 West Chapman Avenue, Suite 7200, Orange, CA 92868, USA
| | - Allen Rojhani
- Department of Urology, University of California, Irvine, 3800 West Chapman Avenue, Suite 7200, Orange, CA 92868, USA
| | - Jaime Altamirano-Villarroel
- Department of Urology, University of California, Irvine, 3800 West Chapman Avenue, Suite 7200, Orange, CA 92868, USA
| | - Jaime Landman
- Department of Urology, University of California, Irvine, 3800 West Chapman Avenue, Suite 7200, Orange, CA 92868, USA
| |
Collapse
|
2
|
Sivasubramani S, Paikaray B, Kuchibhotla M, Haldar A, Murapaka C, Acharyya A. Skyrmion based 3D low complex runtime reconfigurable architecture design methodology of universal logic gate. NANOTECHNOLOGY 2023; 34:13LT01. [PMID: 36584387 DOI: 10.1088/1361-6528/acaf32] [Citation(s) in RCA: 1] [Impact Index Per Article: 0.5] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Received: 08/18/2022] [Accepted: 12/29/2022] [Indexed: 06/17/2023]
Abstract
In this study, we introduce the area efficient low complex runtime reconfigurable architecture design methodology based on Skyrmion logic for universal logic gate (ULG) i.e. NOR/NAND implementation using micromagnetic simulations. We have modelled the two input 3D device structure using bilayer ferromagnet/heavy metal where the magnetic tunnel junctions inject and detect the input and output skyrmions by exploiting the input reversal mechanism. The implementation of NOR and NAND is performed using this same device where it is reconfigured runtime with enhanced tunability by the ON and OFF state of current passing through a non magnetic metallic gate respectively. This gate acts as a barrier for skyrmion motion (additional control mechanism) to realize the required Skyrmion logic output states. To the best of authors's knowledge the boolean optimizations and the mapping logic have been presented for the first time to demonstrate the functionalities of the NOR/NAND implementation. This proposed architecture design methodology of ULG leads to reduced device footprint with regard to the number of thin film structures proposed, low complexity in terms of fabrication and also providing runtime reconfigurability to reduce the number of physical designs to achieve all truth table entries (∼75% device footprint reduction). The proposed 3D ULG architecture design benefits from the miniaturization resulting in opening up a new perspective for magneto-logic devices.
Collapse
Affiliation(s)
- Santhosh Sivasubramani
- Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology (IIT) Hyderabad, 502284, India
| | - Bibekananda Paikaray
- Department of Materials Science and Metallurgical Engineering, Indian Institute of Technology (IIT) Hyderabad, 502284, India
| | - Mahathi Kuchibhotla
- Department of Physics, Indian Institute of Technology (IIT) Hyderabad, 502284, India
| | - Arabinda Haldar
- Department of Physics, Indian Institute of Technology (IIT) Hyderabad, 502284, India
| | - Chandrasekhar Murapaka
- Department of Materials Science and Metallurgical Engineering, Indian Institute of Technology (IIT) Hyderabad, 502284, India
| | - Amit Acharyya
- Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology (IIT) Hyderabad, 502284, India
| |
Collapse
|
3
|
Mattela V, Debroy S, Sivasubramani S, Acharyya A. Interlayer exchange couple based reliable and robust 3-input adder design methodology. NANOTECHNOLOGY 2021; 32:325201. [PMID: 33915527 DOI: 10.1088/1361-6528/abfcfc] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Received: 11/25/2020] [Accepted: 04/29/2021] [Indexed: 06/12/2023]
Abstract
In this paper, a novel inter-layer exchange coupled (IEC) based 3-input full adder design methodology is proposed and subsequently the architecture has been implemented on the widely accepted micromagnetic OOMMF platform. The impact of temperature on the IEC coupled full-adder design has been analyzed up to Curie temperature. It was observed that even up to Curie temperature the IEC based adder design was able to operate at sub-50 nm as contrast to dipole coupled adder design which failed at 5 K for sub 50 nm. Simulation results obtained from OOMMF micromagnetic simulator shows, the IEC based adder design was at a lower energy state as compared to the dipole coupled adder indicating a more stable system and as the temperature of the design was increased, the total energy increased resulting in reduced stability. Potential explanation for the thermodynamic stability of IEC model lies in its energetically favored architecture, such that the total energy was lower than its dipole coupled counterparts. IEC architecture demonstrates supremacy in reliability and strength enabling NML to march towards beyond CMOS devices.
Collapse
Affiliation(s)
- Venkat Mattela
- Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology, Hyderabad, India
| | - Sanghamitra Debroy
- Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology, Hyderabad, India
| | - Santhosh Sivasubramani
- Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology, Hyderabad, India
| | - Amit Acharyya
- Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology, Hyderabad, India
| |
Collapse
|
4
|
Sivasubramani S, Debroy S, Acharyya A. Area efficient in-plane nanomagnetic multiplier and convolution architecture design. NANO EXPRESS 2021. [DOI: 10.1088/2632-959x/abf524] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 11/12/2022]
Abstract
Abstract
In this study, we propose a nanomagnetic logic (NML) based 2 bit multiplier architecture design for the first time to the best of author’s knowledge. This complex combinational logic (nanomagnetic multiplier) design proposed is built by exploiting shape, positional hybrid anisotropy and the ferromagnetically coupled fixed input majority gate. Subsequently, we extend this proposed multiplier architecture along with the NML adder architecture in introducing NML based convolution architecture design which is efficient in terms of number of nanomagnets, majority gates and clock-cycles. The proposed NML design yields ∼21%–72%, ∼26%–42%, ∼36%–63%, and ∼20%–68%, reduction in the required number of nanomagnets, majority gate, clock cycles and energy compared to the state-of-the-art designs.
Collapse
|
5
|
Mattela V, Debroy S, Sivasubramani S, Acharyya A. A novel and reliable interlayer exchange coupled nanomagnetic universal logic gate design. NANOTECHNOLOGY 2021; 32:095205. [PMID: 33197897 DOI: 10.1088/1361-6528/abcac9] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 06/11/2023]
Abstract
In this paper, we propose an interlayer exchange coupling (IEC) based 3D universal NAND/NOR gate design methodology for the reliable and robust implementation of nanomagnetic logic design as compared to the state-of-the art architectures. Owing to stronger coupling scheme as compared to the conventional dipole coupling, the random flip of the states of the nanomagnets (i.e. the soft error) is reduced resulting in greater scalability and better data retention at the deep sub-micron level. Results obtained from Object Oriented Micromagnetic Framework micromagnetic simulation show even at a Curie temperature of the nanomagnets coupled through IEC, the logic function works properly as opposed to dipole coupled nanomagnets which fails at 5 K when scaled down to sub 50 nm. Contemplating the fabrication challenges, the robustness of the IEC design was studied for structural defects, positional misalignment, shape, and size variations. This proposed 3D universal gate design methodology benefits from the miniaturization of nanomagnets as well as reduces the effect of thermally induced errors resulting in opening up a new perspective for nanomagnet based design in magneto-logic devices.
Collapse
Affiliation(s)
- Venkat Mattela
- Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology, Hyderabad, India
| | - Sanghamitra Debroy
- Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology, Hyderabad, India
| | - Santhosh Sivasubramani
- Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology, Hyderabad, India
| | - Amit Acharyya
- Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology, Hyderabad, India
| |
Collapse
|