Speech processing for cochlear implants with the discrete wavelet transform: feasibility study and performance evaluation

A recursive wavelet-based strategy for real-time cochlear implant speech processing on PDA platforms

This paper presents a wavelet-based speech coding strategy for cochlear implants. In addition, it describes the real-time implementation of this strategy on a personal digital assistant (PDA) platform. Three wavelet packet decomposition tree structures are considered and their performance in terms of computational complexity, spectral leakage, fixed-point accuracy, and real-time processing are compared to other commonly used strategies in cochlear implants. A real-time mechanism is introduced for updating the wavelet coefficients recursively. It is shown that the proposed strategy achieves higher analysis rates than the existing strategies while being able to run in real time on a PDA platform. In addition, it is shown that this strategy leads to a lower amount of spectral leakage. The PDA implementation is made interactive to allow users to easily manipulate the parameters involved and study their effects.

Efficient algorithm development of CIS speech processing strategy for cochlear implants

Continuous Interleaved Sampling (CIS) is one of the most useful and famous speech processing strategies used in Cochlear Implant speech processors. However, algorithm realization in hardware is a laborious task due to high computation cost of the algorithm. Real-time issues and low-power design demands an optimized realization of algorithm. This paper proposes two techniques to cut the computation cost of CIS by using polyphase filters and by implementing the complete algorithm in frequency domain. About 70% reduction in computation cost can be achieved by using multi-rate, multistage filters; whereas computation cost decreases by a factor of five when the whole algorithm is implemented in frequency domain. Evaluation of the algorithm is done by a laboratory designed algorithm development and evaluation platform. Algorithm flow diagrams and their computation details have been given for comparison. Utilizing the given techniques can remarkably reduce the processor load without any compromise on quality.