A Low-Power Asynchronous Step-Down DC-DC Converter for Implantable Devices

A 0.35-V 240-μW Fast-Lock and Low-Phase-Noise Frequency Synthesizer for Implantable Biomedical Applications

For implantable frequency synthesizers, realizing ultra-low voltage (ULV) and low power in addition to meeting PLL targets, fast lock and low phase noise, poses a difficult challenge. This paper presents techniques to achieve PLL targets as well as ULV and low power in the same chip through the use of a regular CMOS technology node. A curvature-PFD technique achieves both faster locking and lower jitter compared with conventional techniques. A two-step switching technique substantially reduces the power consumption in current mirrors and reduce noise when switching from a charge pump. Leakage analysis and subthreshold-leakage-reduction technique reduce reference spur and jitter to the voltage-controlled oscillator (VCO). A dither technique randomizes and averages reference spurs. The proposed chip was implemented in 90-nm CMOS technology; the 0.35-V medical-band frequency synthesizer consumes 238-μW power while generating output clock of 401.8 to 431.31-MHz and exhibiting a phase noise of -105.7 dBc/Hz at 1-MHz frequency offset with 20 μs locking time.

Reference-Free Dynamic Voltage Scaler Based on Swapping Switched-Capacitors

This paper introduces a reference-free, scalable, and energy-efficient dynamic voltage scaler (DVS) that can be reconfigured for multiple outputs. The proposed DVS employs a novel swapping switched-capacitor (SSC) technique, which can generate target output voltages with higher resolution and smaller ripple voltages than the conventional voltage scalers based on switched-capacitors. The proposed DVS consists of a cascaded 2:1 converter based on swapping capacitors, which is essential to achieve both very small voltage ripple and fine-grain conversion ratios. One of the serious drawbacks of the conventional voltage scalers is the need for external reference voltages to maintain the target output voltage. The proposed SSC; however, eliminates the needs for any reference voltages. This significant benefit is achieved by the self-charging ability of the SSC, which can recharge all its capacitors to the configured voltage by simply swapping the two capacitors in each stage. The proposed SSC-DVS was designed with a resolution of 16 output levels and implemented using a 130 nm CMOS (Complementary Metal Oxide semiconductor) process. We conducted measured results and post-layout simulations with an input voltage of 1.5 V to produce an output voltage range of 0.085–1.4 V, which demonstrated a power efficiency of 85% for a load current of 550 µA with a voltage ripple of as low as 2.656 mV for a 2 KΩ resistor load.

A 0.04 mm (2) Buck-Boost DC-DC Converter for Biomedical Implants Using Adaptive Gain and Discrete Frequency Scaling Control

This paper presents the design of a reconfigurable buck-boost switched-capacitor DC-DC converter suitable for use in a wide range of biomedical implants. The proposed converter has an extremely small footprint and uses a novel control method that allows coarse and fine control of the output voltage. The converter uses adaptive gain control, discrete frequency scaling and pulse-skipping schemes to regulate the power delivered to a range of output voltages and loads. Adaptive gain control is used to implement variable switching gain ratios from a reconfigurable power stage and thereby make coarse steps in output voltage. A discrete frequency scaling controller makes discrete changes in switching frequency to vary the power delivered to the load and perform fine tuning when the output voltage is within 10% of the target output voltage. The control architecture is predominately digital and it has been implemented as part of a fully-integrated switched-capacitor converter design using a standard bulk CMOS 0.18 μm process. Measured results show that the converter has an output voltage range of 1.0 to 2.2 V, can deliver up to 7.5 mW of load power and efficiency up to 75% using an active area of only 0.04 mm (2), which is significantly smaller than that of other designs. This low-area, low-complexity reconfigurable power converter can support low-power circuits in biomedical implant applications.

A PWM Buck Converter With Load-Adaptive Power Transistor Scaling Scheme Using Analog-Digital Hybrid Control for High Energy Efficiency in Implantable Biomedical Systems

We report a pulse width modulation (PWM) buck converter that is able to achieve a power conversion efficiency (PCE) of > 80% in light loads 100 μA) for implantable biomedical systems. In order to achieve a high PCE for the given light loads, the buck converter adaptively reconfigures the size of power PMOS and NMOS transistors and their gate drivers in accordance with load currents, while operating at a fixed frequency of 1 MHz. The buck converter employs the analog-digital hybrid control scheme for coarse/fine adjustment of power transistors. The coarse digital control generates an approximate duty cycle necessary for driving a given load and selects an appropriate width of power transistors to minimize redundant power dissipation. The fine analog control provides the final tuning of the duty cycle to compensate for the error from the coarse digital control. The mode switching between the analog and digital controls is accomplished by a mode arbiter which estimates the average of duty cycles for the given load condition from limit cycle oscillations (LCO) induced by coarse adjustment. The fabricated buck converter achieved a peak efficiency of 86.3% at 1.4 mA and > 80% efficiency for a wide range of load conditions from 45 μA to 4.1 mA, while generating 1 V output from 2.5-3.3 V supply. The converter occupies 0.375 mm(2) in 0.18 μm CMOS processes and requires two external components: 1.2 μF capacitor and 6.8 μH inductor.

Concept Design for a 1-Lead Wearable/Implantable ECG Front-End: Power Management

Power supply quality and stability are critical for wearable and implantable biomedical applications. For this reason we have designed a reconfigurable switched-capacitor DC-DC converter that, aside from having an extremely small footprint (with an active on-chip area of only 0.04 mm²), uses a novel output voltage control method based upon a combination of adaptive gain and discrete frequency scaling control schemes. This novel DC-DC converter achieves a measured output voltage range of 1.0 to 2.2 V with power delivery up to 7.5 mW with 75% efficiency. In this paper, we present the use of this converter as a power supply for a concept design of a wearable (15 mm × 15 mm) 1-lead ECG front-end sensor device that simultaneously harvests power and communicates with external receivers when exposed to a suitable RF field. Due to voltage range limitations of the fabrication process of the current prototype chip, we focus our analysis solely on the power supply of the ECG front-end whose design is also detailed in this paper. Measurement results show not just that the power supplied is regulated, clean and does not infringe upon the ECG bandwidth, but that there is negligible difference between signals acquired using standard linear power-supplies and when the power is regulated by our power management chip.

A mm-sized wirelessly powered and remotely controlled locomotive implant

A wirelessly powered and controlled implantable device capable of locomotion in a fluid medium is presented. Two scalable low-power propulsion methods are described that achieve roughly an order of magnitude better performance than existing methods in terms of thrust conversion efficiency. The wireless prototype occupies 0.6 mm × 1 mm in 65 nm CMOS with an external 2 mm × 2 mm receive antenna. The IC consists of a matching network, a rectifier, a bandgap reference, a regulator, a demodulator, a digital controller, and high-current drivers that interface directly with the propulsion system. It receives 500 μW from a 2 W 1.86 GHz power signal at a distance of 5 cm. Asynchronous pulse-width modulation on the carrier allows for data rates from 2.5-25 Mbps with energy efficiency of 0.5 pJ/b at 10 Mbps. The received data configures the propulsion system drivers, which are capable of driving up to 2 mA at 0.2 V and can achieve speed of 0.53 cm/sec in a 0.06 T magnetic field.