Implantable stimulator for epileptic seizure suppression with loading impedance adaptability

Charge-Mode Neural Stimulator With a Capacitor-Reuse Residual Charge Detector and Active Charge Balancing for Epileptic Seizure Suppression

This study proposes a charge-mode neural stimulator for electrical stimulation systems that utilizes a capacitor-reuse technique with a residual charge detector and achieves active charge balancing simultaneously. The design is mainly used for epilepsy suppression systems to achieve real-time symptom relief during seizures. A charge-mode stimulator is adopted in consideration of the complexity of circuit design, the high voltage tolerance of transistors, and system integration requirements in the future. The residual charge detector allows users to understand the current stimulus situation, enabling them to make optimal adjustments to the stimulation parameters. On the basis of the information on actual stimulation charge, active charge balancing can effectively prevent the accumulation of mismatched charges on electrode impedance. The capacitor- and phase-reuse techniques help realize high integration of the overall stimulator circuit in consideration of the commonality of the use of a capacitor and charging/discharging phase in the stimulation circuit and charge detector. The proposed charge-mode neural stimulator is implemented in a TSMC 0.18 µm 1P6M CMOS process with a core area of 0.2127 mm2. Measurement results demonstrate the accuracy of the stimulation's functionality and the programmable stimulus parameters. The effectiveness of the proposed charge-mode neural stimulator for epileptic seizure suppression is verified through animal experiments.

A Neural Recording and Stimulation Chip with Artifact Suppression for Biomedical Devices

This paper presents chip implementation of the integrated neural recording and stimulation system with stimulation-induced artifact suppression. The implemented chip consists of low-power neural recording circuits, stimulation circuits, and action potential detection circuits. These circuits constitute a closed-loop simultaneous neural recording and stimulation system for biomedical devices, and a proposed artifact suppression technique is used in the system. Moreover, this paper also presents the measurement and experiment results of the implemented 4-to-4 channel neural recording and stimulation chip with 0.18 µm CMOS technology. The function and efficacy of simultaneous neural recording and stimulation is validated in both in vivo and animal experiments.

Advances in Neural Recording and Stimulation Integrated Circuits

In the past few decades, driven by the increasing demands in the biomedical field aiming to cure neurological diseases and improve the quality of daily lives of the patients, researchers began to take advantage of the semiconductor technology to develop miniaturized and power-efficient chips for implantable applications. The emergence of the integrated circuits for neural prosthesis improves the treatment process of epilepsy, hearing loss, retinal damage, and other neurological diseases, which brings benefits to many patients. However, considering the safety and accuracy in the neural prosthesis process, there are many research directions. In the process of chip design, designers need to carefully analyze various parameters, and investigate different design techniques. This article presents the advances in neural recording and stimulation integrated circuits, including (1) a brief introduction of the basics of neural prosthesis circuits and the repair process in the bionic neural link, (2) a systematic introduction of the basic architecture and the latest technology of neural recording and stimulation integrated circuits, (3) a summary of the key issues of neural recording and stimulation integrated circuits, and (4) a discussion about the considerations of neural recording and stimulation circuit architecture selection and a discussion of future trends. The overview would help the designers to understand the latest performances in many aspects and to meet the design requirements better.

An Ultra High-Frequency 8-Channel Neurostimulator Circuit With [Formula: see text] Peak Power Efficiency

In order to recruit neurons in excitable tissue, constant current neural stimulators are commonly used. Recently, ultra high-frequency (UHF) stimulation has been proposed and proven to have the same efficacy as constant-current stimulation. UHF stimulation uses a fundamentally different way of activating the tissue: each stimulation phase is made of a burst of current pulses with adjustable amplitude injected into the tissue at a high (e.g., [Formula: see text]) frequency. This paper presents the design, integrated circuit (IC) implementation, and measurement results of a power efficient multichannel UHF neural stimulator. The core of the neurostimulator is based on our previously proposed architecture of an inductor-based buck-boost dc-dc converter without the external output capacitor. The ultimate goal of this work is to increase the power efficiency of the UHF stimulator for multiple-channel operation, while keeping the number of external components minimal. To this end, a number of novel approaches were employed in the integrated circuit design domain. More specifically, a novel zero-current detection scheme is proposed. It allows to remove the freewheel diode typically used in dc-dc converters to prevent current to flow back from the load to the inductor. Furthermore, a gate-driver circuit is implemented which allows the use of thin gate-oxide transistors as high-voltage switches. By doing so, and exploiting the fundamental working principle of the proposed current-controlled UHF stimulator, the need for a high-voltage supply is eliminated and the stimulator is powered up from a [Formula: see text] input voltage. Both the current detection technique and the gate driving circuit of the current implementation allow to boost the power efficiency up to [Formula: see text] when compared to previous UHF stimulator works. A peak power efficiency of [Formula: see text] is achieved, while 8 independent channels with 16 fully configurable electrodes are used. The circuit is implemented in a [Formula: see text] HV process, and the total chip area is [Formula: see text].

A new description of epileptic seizures based on dynamic analysis of a thalamocortical model

Increasing evidence suggests that the brain dynamics can be interpreted from the viewpoint of nonlinear dynamical systems. The aim of this paper is to investigate the behavior of a thalamocortical model from this perspective. The model includes both cortical and sensory inputs that can affect the dynamic nature of the model. Driving response of the model subjected to various harmonic stimulations is considered to identify the effects of stimulus parameters on the cortical output. Detailed numerical studies including phase portraits, Poincare maps and bifurcation diagrams reveal a wide range of complex dynamics including period doubling and chaos in the output. Transition between different states can occur as the stimulation parameters are changed. In addition, the amplitude jump phenomena and hysteresis are shown to be possible as a result of the bending in the frequency response curve. These results suggest that the jump phenomenon due to the brain nonlinear resonance can be responsible for the transitions between ictal and interictal states.

A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process

A new digitally dynamic power supply technique for 16-channel 12-V-tolerant stimulator is proposed and realized in a 0.18-μm 1.8-V/3.3-V CMOS process. The proposed stimulator uses four stacked transistors as the pull-down switch and pull-up switch to withstand 4 times the nominal supply voltage (4 × V _DD). With the dc input voltage of 3.3 V, the regulated three-stage charge pump, which is capable of providing 11.3-V voltage at 3-mA loading current, achieves dc conversion efficiency of up to 69% with 400-pF integrated capacitance. Power consumption is reduced by implementing the regulated charge pump to provide a dynamic dc output voltage with a 0.5-V step. The proposed digitally dynamic power supply technique, which is implemented by using a p-type metal oxide semiconductor (PMOS) inverter with pull-down current source and digital controller, greatly improves the power efficiency of a system. The silicon area of the stimulator is approximately 3.5 mm² for a 16-channel implementation. The functionalities of the proposed stimulator have been successfully verified through animal test.

Compact, Energy-Efficient High-Frequency Switched Capacitor Neural Stimulator With Active Charge Balancing

Safety and energy efficiency are two major concerns for implantable neural stimulators. This paper presents a novel high-frequency, switched capacitor (HFSC) stimulation and active charge balancing scheme, which achieves high energy efficiency and well-controlled stimulation charge in the presence of large electrode impedance variations. Furthermore, the HFSC can be implemented in a compact size without any external component to simultaneously enable multichannel stimulation by deploying multiple stimulators. The theoretical analysis shows significant benefits over the constant-current and voltage-mode stimulation methods. The proposed solution was fabricated using a 0.18 μm high-voltage technology, and occupies only 0.035 mm² for a single stimulator. The measurement result shows 50% peak energy efficiency and confirms the effectiveness of active charge balancing to prevent the electrode dissolution.

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

This paper presents a 4 × V_DD neuro-stimulator in a 0.18- μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000- μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.

A 1.83 μJ/Classification, 8-Channel, Patient-Specific Epileptic Seizure Classification SoC Using a Non-Linear Support Vector Machine

A non-linear support vector machine (NLSVM) seizure classification SoC with 8-channel EEG data acquisition and storage for epileptic patients is presented. The proposed SoC is the first work in literature that integrates a feature extraction (FE) engine, patient specific hardware-efficient NLSVM classification engine, 96 KB SRAM for EEG data storage and low-noise, high dynamic range readout circuits. To achieve on-chip integration of the NLSVM classification engine with minimum area and energy consumption, the FE engine utilizes time division multiplexing (TDM)-BPF architecture. The implemented log-linear Gaussian basis function (LL-GBF) NLSVM classifier exploits the linearization to achieve energy consumption of 0.39 μ J/operation and reduces the area by 28.2% compared to conventional GBF implementation. The readout circuits incorporate a chopper-stabilized DC servo loop to minimize the noise level elevation and achieve noise RTI of 0.81 μ Vrms for 0.5-100 Hz bandwidth with an NEF of 4.0. The 5 × 5 mm (2) SoC is implemented in a 0.18 μm 1P6M CMOS process consuming 1.83 μ J/classification for 8-channel operation. SoC verification has been done with the Children's Hospital Boston-MIT EEG database, as well as with a specific rapid eye-blink pattern detection test, which results in an average detection rate, average false alarm rate and latency of 95.1%, 0.94% (0.27 false alarms/hour) and 2 s, respectively.

A Power-Efficient Multichannel Neural Stimulator Using High-Frequency Pulsed Excitation From an Unfiltered Dynamic Supply

This paper presents a neural stimulator system that employs a fundamentally different way of stimulating neural tissue compared to classical constant current stimulation. A stimulation pulse is composed of a sequence of current pulses injected at a frequency of 1 MHz for which the duty cycle is used to control the stimulation intensity. The system features 8 independent channels that connect to any of the 16 electrodes at the output. A sophisticated control system allows for individual control of each channel's stimulation and timing parameters. This flexibility makes the system suitable for complex electrode configurations and current steering applications. Simultaneous multichannel stimulation is implemented using a high frequency alternating technique, which reduces the amount of electrode switches by a factor 8. The system has the advantage of requiring a single inductor as its only external component. Furthermore it offers a high power efficiency, which is nearly independent on both the voltage over the load as well as on the number of simultaneously operated channels. Measurements confirm this: in multichannel mode the power efficiency can be increased for specific cases to 40% compared to 20% that is achieved by state-of-the-art classical constant current stimulators with adaptive power supply.

An 81.6 μW FastICA processor for epileptic seizure detection

To improve the performance of epileptic seizure detection, independent component analysis (ICA) is applied to multi-channel signals to separate artifacts and signals of interest. FastICA is an efficient algorithm to compute ICA. To reduce the energy dissipation, eigenvalue decomposition (EVD) is utilized in the preprocessing stage to reduce the convergence time of iterative calculation of ICA components. EVD is computed efficiently through an array structure of processing elements running in parallel. Area-efficient EVD architecture is realized by leveraging the approximate Jacobi algorithm, leading to a 77.2% area reduction. By choosing proper memory element and reduced wordlength, the power and area of storage memory are reduced by 95.6% and 51.7%, respectively. The chip area is minimized through fixed-point implementation and architectural transformations. Given a latency constraint of 0.1 s, an 86.5% area reduction is achieved compared to the direct-mapped architecture. Fabricated in 90 nm CMOS, the core area of the chip is 0.40 mm(2). The FastICA processor, part of an integrated epileptic control SoC, dissipates 81.6 μW at 0.32 V. The computation delay of a frame of 256 samples for 8 channels is 84.2 ms. Compared to prior work, 0.5% power dissipation, 26.7% silicon area, and 3.4 × computation speedup are achieved. The performance of the chip was verified by human dataset.