Design of a Closed-Loop, Bidirectional Brain Machine Interface System With Energy Efficient Neural Feature Extraction and PID Control

Self-adaptive rotational electromagnetic energy generation as an alternative to triboelectric and piezoelectric transductions

Triboelectric and piezoelectric energy harvesters can hardly power most microelectronic systems. Rotational electromagnetic harvesters are very promising alternatives, but their performance is highly dependent on the varying mechanical sources. This study presents an innovative approach to significantly increase the performance of rotational harvesters, based on dynamic coil switching strategies for optimization of the coil connection architecture during energy generation. Both analytical and experimental validations of the concept of self-adaptive rotational harvester were carried out. The adaptive harvester was able to provide an average power increase of 63.3% and 79.5% when compared to a non-adaptive 16-coil harvester for harmonic translation and harmonic swaying excitations, respectively, and 83.5% and 87.2% when compared to a non-adaptive 8-coil harvester. The estimated energy conversion efficiency was also enhanced from ~80% to 90%. This study unravels an emerging technological approach to power a wide range of applications that cannot be powered by other vibrationally driven harvesters.

Anti-artifacts techniques for neural recording front-ends in closed-loop brain-machine interface ICs

In recent years, thanks to the development of integrated circuits, clinical medicine has witnessed significant advancements, enabling more efficient and intelligent treatment approaches. Particularly in the field of neuromedical, the utilization of brain-machine interfaces (BMI) has revolutionized the treatment of neurological diseases such as amyotrophic lateral sclerosis, cerebral palsy, stroke, or spinal cord injury. The BMI acquires neural signals via recording circuits and analyze them to regulate neural stimulator circuits for effective neurological treatment. However, traditional BMI designs, which are often isolated, have given way to closed-loop brain-machine interfaces (CL-BMI) as a contemporary development trend. CL-BMI offers increased integration and accelerated response speed, marking a significant leap forward in neuromedicine. Nonetheless, this advancement comes with its challenges, notably the stimulation artifacts (SA) problem inherent to the structural characteristics of CL-BMI, which poses significant challenges on the neural recording front-ends (NRFE) site. This paper aims to provide a comprehensive overview of technologies addressing artifacts in the NRFE site within CL-BMI. Topics covered will include: (1) understanding and assessing artifacts; (2) exploring the impact of artifacts on traditional neural recording front-ends; (3) reviewing recent technological advancements aimed at addressing artifact-related issues; (4) summarizing and classifying the aforementioned technologies, along with an analysis of future trends.

Design of a Sleep Modulation System with FPGA-Accelerated Deep Learning for Closed-loop Stage-Specific In-Phase Auditory Stimulation

Closed-loop sleep modulation is an emerging research paradigm to treat sleep disorders and enhance sleep benefits. However, two major barriers hinder the widespread application of this research paradigm. First, subjects often need to be wire-connected to rack-mount instrumentation for data acquisition, which negatively affects sleep quality. Second, conventional real-time sleep stage classification algorithms give limited performance. In this work, we conquer these two limitations by developing a sleep modulation system that supports closed-loop operations on the device. Sleep stage classification is performed using a lightweight deep learning (DL) model accelerated by a low-power field-programmable gate array (FPGA) device. The DL model uses a single channel electroencephalogram (EEG) as input. Two convolutional neural networks (CNNs) are used to capture general and detailed features, and a bidirectional long-short-term memory (LSTM) network is used to capture time-variant sequence features. An 8-bit quantization is used to reduce the computational cost without compromising performance. The DL model has been validated using a public sleep database containing 81 subjects, achieving a state-of-the-art classification accuracy of 85.8% and a F1-score of 79%. The developed model has also shown the potential to be generalized to different channels and input data lengths. Closed-loop in-phase auditory stimulation has been demonstrated on the test bench.

Power-efficientin vivobrain-machine interfaces via brain-state estimation

Objective.Advances in brain-machine interfaces (BMIs) can potentially improve the quality of life of millions of users with spinal cord injury or other neurological disorders by allowing them to interact with the physical environment at their will.Approach.To reduce the power consumption of the brain-implanted interface, this article presents the first hardware realization of anin vivointention-aware interface via brain-state estimation.Main Results.It is shown that incorporating brain-state estimation reduces thein vivopower consumption and reduces total energy dissipation by over 1.8× compared to those of the current systems, enabling longer better life for implanted circuits. The synthesized application-specific integrated circuit (ASIC) of the designed intention-aware multi-unit spike detection system in a standard 180 nm CMOS process occupies 0.03 mm²of silicon area and consumes 0.63 µW of power per channel, which is the least power consumption among the currentin vivoASIC realizations.Significance.The proposed interface is the first practical approach towards realizing asynchronous BMIs while reducing the power consumption of the BMI interface and enhancing neural decoding performance compared to those of the conventional synchronous BMIs.

In vivo neural spike detection with adaptive noise estimation

The ability to reliably detect neural spikes from a relatively large population of neurons contaminated with noise is imperative for reliable decoding of recorded neural information. This article first analyzes the accuracy and feasibility of various potential spike detection techniques for in vivo realizations. Then an accurate and computationally-efficient spike detection module that can autonomously adapt to variations in recording channels' statistics is presented. The accuracy of the chosen candidate spike detection technique is evaluated using both synthetic and real neural recordings. The designed detector also offers the highest decoding performance over two animal behavioral datasets among alternative detection methods. The implementation results of the designed 128-channel spike detection module in a standard 180-nm CMOS process is among the most area and power-efficient spike detection ASICs and operates within the tissue-safe constraints for brain implants, while offering adaptive noise estimation.

Design of PID Controller Based on Echo State Network With Time-Varying Reservoir Parameter

In this article, a new design method based on the echo state network with time-varying reservoir parameter (TVRP-ESN) is proposed to optimize the proportional-integral-derivative (PID) controller parameters for a class of discrete-time systems with time delay. The TVRP-ESN can quickly obtain the PID controller parameters to meet the control performance of the system. According to the network learning and approximation ability of TVRP-ESN, the output weights and the reservoir parameters of TVRP-ESN can be synchronously updated, and then the TVRP-ESN can improve the convergence speed of determining the PID controller parameters. In order to update the output weights and the reservoir parameters of TVRP-ESN, the partial derivative of the system output error is used. Three simulation examples are used to show the effectiveness of the proposed method.

In vivo closed-loop control of a locust's leg using nerve stimulation

Activity of an innervated tissue can be modulated based on an acquired biomarker through feedback loops. How to convert this biomarker into a meaningful stimulation pattern is still a topic of intensive research. In this article, we present a simple closed-loop mechanism to control the mean angle of a locust’s leg in real time by modulating the frequency of the stimulation on its extensor motor nerve. The nerve is interfaced with a custom-designed cuff electrode and the feedback loop is implemented online with a proportional control algorithm, which runs solely on a microcontroller without the need of an external computer. The results show that the system can be controlled with a single-input, single-output feedback loop. The model described in this article can serve as a primer for young researchers to learn about neural control in biological systems before applying these concepts in advanced systems. We expect that the approach can be advanced to achieve control over more complex movements by increasing the number of recorded biomarkers and selective stimulation units.

Algorithm and hardware considerations for real-time neural signal on-implant processing

Objective Various on-workstation neural-spike-based brain machine interface(BMI) systems have reached the point of in-human trials, but on-node and on-implant BMI systems are still under exploration. Such systems are constrained by the area and battery. Researchers should consider the algorithm complexity, available resources, power budgets, CMOS technologies, and the choice of platforms when designing BMI systems. However, the effect of these factors is currently still unclear. Approaches. Here we have proposed a novel real-time 128 channel spike detection algorithm and optimised it on Microcontroller(MCU) and Field Programmable Gate Array(FPGA) platforms towards consuming minimal power and memory/resources. It is presented as a use case to explore the different considerations in system design. Main results. The proposed spike detection algorithm achieved over 97% sensitivity and a smaller than 3% false detection rate. The MCU implementation occupies less than 3KB RAM and consumes 31.5μW/ch. The FPGA platform only occupies 299 logic cells and 3KB RAM for 128 channels and consumes 0.04μW/ch. Significance. On the spike detection algorithm front, we have eliminated the processing bottleneck by reducing the dynamic power consumption to lower than the hardware static power, without sacrificing detection performance. More importantly, we have explored the considerations in algorithm and hardware design with respect to scalability, portability, and costs. These findings can facilitate and guide the future development of real-time on-implant neural signal processing platforms.

Auxiliary controller design and performance comparative analysis in closed-loop brain-machine interface system

Brain-machine interface (BMI) can realize information interaction between the brain and external devices, and yet the control accuracy is limited by the change of electroencephalogram signals. The introduction of auxiliary controller can overcome the above problems, but the performance of different auxiliary controllers is quite different. Hence, in this paper, we comprehensively compare and analyze the performance of different auxiliary controllers to provide a theoretical basis for designing BMI system. The main work includes: (1) designing four kinds of auxiliary controllers based on simultaneous perturbation stochastic approximation-function approximator (SPSA-FA), iterative feedback tuning-PID (IFT-PID), model predictive control (MPC) and model-free control (MFC); (2) based on the model of improved single-joint information transmission, constructing the closed-loop BMI systems with the decoder-based Wiener filter; and (3) comparing their performance in the constructed closed-loop BMI systems for dynamic motion restoration. The results show that the order of tracking accuracy is MPC, IFT-PID, SPSA-FA, MFC, and the order of time consumed is opposite. A good control effectiveness is achieved at the expense of time, so a suitable auxiliary controller should be selected according to the actual requirements.

A System-on-Chip for Closed-loop Optogenetic Sleep Modulation

Stimulation of target neuronal populations using optogenetic techniques during specific sleep stages has begun to elucidate the mechanisms and effects of sleep. To conduct closed-loop optogenetic sleep studies in untethered animals, we designed a fully integrated, low-power system-on-chip (SoC) for real-time sleep stage classification and stage-specific optical stimulation. The SoC consists of a 4-channel analog front-end for recording polysomnography signals, a mixed-signal machine-learning (ML) core, and a 16-channel optical stimulation back-end. A novel ML algorithm and innovative circuit design techniques improved the online classification performance while minimizing power consumption. The SoC was designed and simulated in 180 nm CMOS technology. In an evaluation using an expert labeled sleep database with 20 subjects, the SoC achieves a high sensitivity of 0.806 and a specificity of 0.947 in discriminating 5 sleep stages. Overall power consumption in continuous operation is 97 µW.

A Wireless Electro-Optic Platform for Multimodal Electrophysiology and Optogenetics in Freely Moving Rodents

This paper presents the design and the utilization of a wireless electro-optic platform to perform simultaneous multimodal electrophysiological recordings and optogenetic stimulation in freely moving rodents. The developed system can capture neural action potentials (AP), local field potentials (LFP) and electromyography (EMG) signals with up to 32 channels in parallel while providing four optical stimulation channels. The platform is using commercial off-the-shelf components (COTS) and a low-power digital field-programmable gate array (FPGA), to perform digital signal processing to digitally separate in real time the AP, LFP and EMG while performing signal detection and compression for mitigating wireless bandwidth and power consumption limitations. The different signal modalities collected on the 32 channels are time-multiplexed into a single data stream to decrease power consumption and optimize resource utilization. The data reduction strategy is based on signal processing and real-time data compression. Digital filtering, signal detection, and wavelet data compression are used inside the platform to separate the different electrophysiological signal modalities, namely the local field potentials (1–500 Hz), EMG (30–500 Hz), and the action potentials (300–5,000 Hz) and perform data reduction before transmitting the data. The platform achieves a measured data reduction ratio of 7.77 (for a firing rate of 50 AP/second) and weights 4.7 g with a 100-mAh battery, an on/off switch and a protective plastic enclosure. To validate the performance of the platform, we measured distinct electrophysiology signals and performed optogenetics stimulation in vivo in freely moving rondents. We recorded AP and LFP signals with the platform using a 16-microelectrode array implanted in the primary motor cortex of a Long Evans rat, both in anesthetized and freely moving conditions. EMG responses to optogenetic Channelrhodopsin-2 induced activation of motor cortex via optical fiber were also recorded in freely moving rodents.

Neurochip3: An Autonomous Multichannel Bidirectional Brain-Computer Interface for Closed-Loop Activity-Dependent Stimulation

Toward addressing many neuroprosthetic applications, the Neurochip3 (NC3) is a multichannel bidirectional brain-computer interface that operates autonomously and can support closed-loop activity-dependent stimulation. It consists of four circuit boards populated with off-the-shelf components and is sufficiently compact to be carried on the head of a non-human primate (NHP). NC3 has six main components: (1) an analog front-end with an Intan biophysical signal amplifier (16 differential or 32 single-ended channels) and a 3-axis accelerometer, (2) a digital control system comprised of a Cyclone V FPGA and Atmel SAM4 MCU, (3) a micro SD Card for 128 GB or more storage, (4) a 6-channel differential stimulator with ±60 V compliance, (5) a rechargeable battery pack supporting autonomous operation for up to 24 h and, (6) infrared transceiver and serial ports for communication. The NC3 and earlier versions have been successfully deployed in many closed-loop operations to induce synaptic plasticity and bridge lost biological connections, as well as deliver activity-dependent intracranial reinforcement. These paradigms to strengthen or replace impaired connections have many applications in neuroprosthetics and neurorehabilitation.

Fabrication of Conductive, Adhesive, and Stretchable Agarose-Based Hydrogels for a Wearable Biosensor

Herein, a strategy is proposed to prepare a conductive, self-adhesive, and stretchable agarose gel with the merits of distinct heat resistance, freeze resistance, and long-term moisture retention. To endow the gels with conductivity, monodisperse carbon nanotubes modified by polydopamine are introduced into the gel networks, which promote both conductivity and mechanical strength of the gels. Meanwhile, further addition of glycerol enhances excellent stretchability as well as heating/freezing tolerability and moisture retention of the gels. A wearable biosensor based on the gel is fabricated to record body motions precisely with good biocompatibility, which benefits the development of smart wearable devices.

Light Modulation of Brain and Development of Relevant Equipment

Light modulation plays an important role in understanding the pathology of brain disorders and improving brain function. Optogenetic techniques can activate or silence targeted neurons with high temporal and spatial accuracy and provide precise control, and have recently become a method for quick manipulation of genetically identified types of neurons. Photobiomodulation (PBM) is light therapy that utilizes non-ionizing light sources, including lasers, light emitting diodes, or broadband light. It provides a safe means of modulating brain activity without any irreversible damage and has established optimal treatment parameters in clinical practice. This manuscript reviews 1) how optogenetic approaches have been used to dissect neural circuits in animal models of Alzheimer's disease, Parkinson's disease, and depression, and 2) how low level transcranial lasers and LED stimulation in humans improves brain activity patterns in these diseases. State-of-the-art brain machine interfaces that can record neural activity and stimulate neurons with light have good prospects in the future.

Edge deep learning for neural implants: a case study of seizure detection and prediction

Objective.Implanted devices providing real-time neural activity classification and control are increasingly used to treat neurological disorders, such as epilepsy and Parkinson's disease. Classification performance is critical to identifying brain states appropriate for the therapeutic action (e.g. neural stimulation). However, advanced algorithms that have shown promise in offline studies, in particular deep learning (DL) methods, have not been deployed on resource-restrained neural implants. Here, we designed and optimized three DL models or edge deployment and evaluated their inference performance in a case study of seizure detection.Approach.A deep neural network (DNN), a convolutional neural network (CNN), and a long short-term memory (LSTM) network were designed and trained with TensorFlow to classify ictal, preictal, and interictal phases from the CHB-MIT scalp EEG database. A sliding window based weighted majority voting algorithm was developed to detect seizure events based on each DL model's classification results. After iterative model compression and coefficient quantization, the algorithms were deployed on a general-purpose, off-the-shelf microcontroller for real-time testing. Inference sensitivity, false positive rate (FPR), execution time, memory size, and power consumption were quantified.Main results.For seizure event detection, the sensitivity and FPR for the DNN, CNN, and LSTM models were 87.36%/0.169 h^-1, 96.70%/0.102 h^-1, and 97.61%/0.071 h^-1, respectively. Predicting seizures for early warnings was also feasible. The LSTM model achieved the best overall performance at the expense of the highest power. The DNN model achieved the shortest execution time. The CNN model showed advantages in balanced performance and power with minimum memory requirement. The implemented model compression and quantization achieved a significant saving of power and memory with an accuracy degradation of less than 0.5%.Significance.Inference with embedded DL models achieved performance comparable to many prior implementations that had no time or computational resource limitations. Generic microcontrollers can provide the required memory and computational resources, while model designs can be migrated to application-specific integrated circuits for further optimization and power saving. The results suggest that edge DL inference is a feasible option for future neural implants to improve classification performance and therapeutic outcomes.

A 10.8 µW Neural Signal Recorder and Processor With Unsupervised Analog Classifier for Spike Sorting

Implantable brain machine interfaces for treatment of neurological disorders require on-chip, real-time signal processing of action potentials (spikes). In this work, we present the first spike sorting SoC with integrated neural recording front-end and analog unsupervised classifier. The event-driven, low power spike sorter features a novel hardware-optimized, K-means based algorithm that effectively eliminates duplicate clusters and is implemented using a novel clockless and ADC-less analog architecture. The 1.4 mm² chip is fabricated in a 180-nm CMOS SOI process. The analog front-end achieves a 3.3 μV_rms noise floor over the spike bandwidth (400 - 5000 Hz) and consumes 6.42 μW from a 1.5 V supply. The analog spike sorter consumes 4.35 μW and achieves 93.2% classification accuracy on a widely used synthetic test dataset. In addition, higher than 93% agreement between the chip classification result and that of a standard spike sorting software is observed using pre-recorded real neural signals. Simulations of the implemented spike sorter show robust performance under process-voltage-temperature variations.

Design of a Low Noise Bio-Potential Recorder With High Tolerance to Power-Line Interference Under 0.8 V Power Supply

A bio-potential recorder working under 0.8 V supply voltage with a tunable low-pass filter is proposed in this paper. The prototype is implemented in TSMC 180 nm CMOS technology, featuring a power consumption of 2.27  μW, while preserving a high tolerance of power-line interference (PLI) up to 600 m V_pp, a common-mode rejection ratio (CMRR) of higher than 100 dB, a THD of -65.5 dB, and a noise density of 50 nV/ √{Hz} by employing four new techniques, including 1) low noise chopper modulator, 2) feedback loop based common-mode cancellation loop (CMCL), 3) offset cancellation loop (OCL) with PMOS backgate control scheme, and 4) a very-lower transconductance (VLT) operational transconductance amplifier (OTA) using in the DC-servo-loop (DSL). The measured mid-band gain is 43.3 dB with a high-pass cut-off frequency of 1.2 Hz. The low-pass cut-off frequency can be configured from 650 Hz to 7.5 kHz. The measured input-referred integrated noise is 1.2 uVrms in the frequency band of 1-650 Hz and 4.1 uVrms in the 1 Hz-7.5 kHz frequency band, respectively, leading to a power efficiency factor (PEF) of 7.49 and 7.59.

A Trimodal Wireless Implantable Neural Interface System-on-Chip

A wireless and battery-less trimodal neural interface system-on-chip (SoC), capable of 16-ch neural recording, 8-ch electrical stimulation, and 16-ch optical stimulation, all integrated on a 5 ×  3 mm2 chip fabricated in 0.35-μm standard CMOS process. The trimodal SoC is designed to be inductively powered and communicated. The downlink data telemetry utilizes on-off keying pulse-position modulation (OOK-PPM) of the power carrier to deliver configuration and control commands at 50 kbps. The analog front-end (AFE) provides adjustable mid-band gain of 55-70 dB, low/high cut-off frequencies of 1-100 Hz/10 kHz, and input-referred noise of 3.46 μVrms within 1 Hz-50 kHz band. AFE outputs of every two-channel are digitized by a 50 kS/s 10-bit SAR-ADC, and multiplexed together to form a 6.78 Mbps data stream to be sent out by OOK modulating a 434 MHz RF carrier through a power amplifier (PA) and 6 cm monopole antenna, which form the uplink data telemetry. Optical stimulation has a switched-capacitor based stimulation (SCS) architecture, which can sequentially charge four storage capacitor banks up to 4 V and discharge them in selected μLEDs at instantaneous current levels of up to 24.8 mA on demand. Electrical stimulation is supported by four independently driven stimulating sites at 5-bit controllable current levels in ±(25-775) μA range, while active/passive charge balancing circuits ensure safety. In vivo testing was conducted on four anesthetized rats to verify the functionality of the trimodal SoC.

Fractional order controllers increase the robustness of closed-loop deep brain stimulation systems

We studied the effects of using fractional order proportional, integral, and derivative (PID) controllers in a closed-loop mathematical model of deep brain stimulation. The objective of the controller was to dampen oscillations from a neural network model of Parkinson's disease. We varied intrinsic parameters, such as the gain of the controller, and extrinsic variables, such as the excitability of the network. We found that in most cases, fractional order components increased the robustness of the model multi-fold to changes in the gains of the controller. Similarly, the controller could be set to a fixed set of gains and remain stable to a much larger range, than for the classical PID case, of changes in synaptic weights that otherwise would cause oscillatory activity. The increase in robustness is a consequence of the properties of fractional order derivatives that provide an intrinsic memory trace of past activity, which works as a negative feedback system. Fractional order PID controllers could provide a platform to develop stand-alone closed-loop deep brain stimulation systems.

Recent Advances in Electrical Neural Interface Engineering: Minimal Invasiveness, Longevity, and Scalability

Electrical neural interfaces serve as direct communication pathways that connect the nervous system with the external world. Technological advances in this domain are providing increasingly more powerful tools to study, restore, and augment neural functions. Yet, the complexities of the nervous system give rise to substantial challenges in the design, fabrication, and system-level integration of these functional devices. In this review, we present snapshots of the latest progresses in electrical neural interfaces, with an emphasis on advances that expand the spatiotemporal resolution and extent of mapping and manipulating brain circuits. We include discussions of large-scale, long-lasting neural recording; wireless, miniaturized implants; signal transmission, amplification, and processing; as well as the integration of interfaces with optical modalities. We outline the background and rationale of these developments and share insights into the future directions and new opportunities they enable.

Power Efficiency Comparison of Event-Driven and Fixed-Rate Signal Conversion and Compression for Biomedical Applications

Energy-constrained biomedical recording systems need power-efficient data converters and good signal compression in order to meet the stringent power consumption requirements of many applications. In literature today, typically a SAR ADC in combination with digital compression is used. Recently, alternative event-driven sampling techniques have been proposed that incorporate compression in the ADC, such as level-crossing A/D conversion. This paper describes the power efficiency analysis of such level-crossing ADC (LCADC) and the traditional fixed-rate SAR ADC with simple compression. A model for the power consumption of the LCADC is derived, which is then compared to the power consumption of the SAR ADC with zero-order hold (ZOH) compression for multiple biosignals (ECG, EMG, EEG, and EAP). The LCADC is more power efficient than the SAR ADC up to a cross-over point in quantizer resolution (for example 8 bits for an EEG signal). This cross-over point decreases with the ratio of the maximum to average slope in the signal of the application. It also changes with the technology and design techniques used. The LCADC is thus suited for low to medium resolution applications. In addition, the event-driven operation of an LCADC results in fewer data to be transmitted in a system application. The event-driven LCADC without timer and with single-bit quantizer achieves a reduction in power consumption at system level of two orders of magnitude, an order of magnitude better than the SAR ADC with ZOH compression. At system level, the LCADC thus offers a big advantage over the SAR ADC.

Charge-Redistribution Based Quadratic Operators for Neural Feature Extraction

This paper presents a SAR converter based mixed-signal multiplier for the feature extraction of neural signals using quadratic operators. After a thorough analysis of design principles and circuit-level aspects, the proposed architecture is explored for the implementation of two quadratic operators often used for the characterization of neural activity, the moving average energy (MAE) operator and the nonlinear energy operator (NEO). Programmable chips for both operators have been implemented in a HV-180 nm CMOS process. Experimental results confirm their suitability for energy computation and action potential detection and the accomplished area×power performance is compared to prior art. The MAE and NEO prototypes, at a sampling rate of 30kS/s, consume 116 nW and 178 nW, respectively, and digitize both the input neural signal and the operator outcome, with no need for digital multipliers.

An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces

This article presents an energy-efficient electrocorticography (ECoG) array architecture for fully-implantable brain machine interface systems. A novel dual-mode analog signal processing method is introduced that extracts neural features from high- γ band (80-160 Hz) at the early stages of signal acquisition. Initially, brain activity across the full-spectrum is momentarily observed to compute the feature weights in the digital back-end during full-band mode operation. Subsequently, these weights are fed back to the front-end and the system reverts to base-band mode to perform feature extraction. This approach utilizes a distinct optimized signal pathway based on power envelope extraction, resulting in 1.72× power reduction in the analog blocks and up to 50× potential power savings for digitization and processing (implemented off-chip in this article). A prototype incorporating a 32-channel ultra-low power signal acquisition front-end is fabricated in 180 nm CMOS process with 0.8 V supply. This chip consumes 1.05  μW (0.205  μW for feature extraction only) power and occupies 0.245 [Formula: see text] die area per channel. The chip measurement shows better than 76.5-dB common-mode rejection ratio (CMRR), 4.09 noise efficiency factor (NEF), and 10.04 power efficiency factor (PEF). In-vivo human tests have been carried out with electroencephalography and ECoG signals to validate the performance and dual-mode operation in comparison to commercial acquisition systems.

The Neural Engine: A Reprogrammable Low Power Platform for Closed-Loop Optogenetics

Brain-machine Interfaces (BMI) hold great potential for treating neurological disorders such as epilepsy. Technological progress is allowing for a shift from open-loop, pacemaker-class, intervention towards fully closed-loop neural control systems. Low power programmable processing systems are therefore required which can operate within the thermal window of 2° C for medical implants and maintain long battery life. In this work, we have developed a low power neural engine with an optimized set of algorithms which can operate under a power cycling domain. We have integrated our system with a custom-designed brain implant chip and demonstrated the operational applicability to the closed-loop modulating neural activities in in-vitro and in-vivo brain tissues: the local field potentials can be modulated at required central frequency ranges. Also, both a freely-moving non-human primate (24-hour) and a rodent (1-hour) in-vivo experiments were performed to show system reliable recording performance. The overall system consumes only 2.93 mA during operation with a biological recording frequency 50 Hz sampling rate (the lifespan is approximately 56 hours). A library of algorithms has been implemented in terms of detection, suppression and optical intervention to allow for exploratory applications in different neurological disorders. Thermal experiments demonstrated that operation creates minimal heating as well as battery performance exceeding 24 hours on a freely moving rodent. Therefore, this technology shows great capabilities for both neuroscience in-vitro/in-vivo applications and medical implantable processing units.

A 25 Mbps, 12.4 pJ/b DQPSK Backscatter Data Uplink for the NeuroDisc Brain-Computer Interface

Wireless brain-computer interfaces (BCIs) are used to study neural activity in freely moving non-human primates (NHPs). However, the high energy consumption of conventional active radios is proving to be an obstacle as research drives for wireless BCIs that can provide continuous high-rate data uplinks for longer durations (i.e. multiple days). We present a differential quadrature phase shift keying (DQPSK) backscatter uplink for the NeuroDisc BCI as an alternative to active radios. The uplink achieves a 25 Mbps throughput while operating in the 915 MHz industrial, scientific, and medical (ISM) band. The DQPSK backscatter modulator was measured to have an error-vector magnitude (EVM) of 9.7% and a measured power consumption of 309  μW during continuous, full-rate transmissions, yielding an analog communication efficiency of 12.4 pJ/bit. The NeuroDisc is capable of recording 16 channels of neural data with 16-bit resolution at up to 20 kSps per channel with a measured input-referred noise of 2.35  μV. In previous work, we demonstrated the DQPSK backscatter uplink, but bandwidth constraints in the signal chain limited the uplink rate to 6.25 Mbps and the neural sampling rate to 5 kSps. This work provides new innovations to increase the bandwidth of the system, including an ultra-high frequency (UHF) antenna design with a -10 dB return loss bandwidth of 12.5 MHz and a full-duplex receiver with an average self-jammer cancellation of 89 dB. We present end-to-end characterization of the NeuroDisc and validate the backscatter uplink using pre-recorded neural data as well as in vivo recordings from a pigtail macaque.

A Wireless Electro-Optic Headstage With a 0.13- μm CMOS Custom Integrated DWT Neural Signal Decoder for Closed-Loop Optogenetics

We present a wireless electro-optic headstage that uses a 0.13- μm CMOS custom integrated circuit (IC) implementing a digital neural decoder (ND-IC) for enabling real-time closed-loop (CL) optogenetics. The ND-IC processes the neural activity data using three digital cores: 1) the detector core detects and extracts the action potential (AP) of individual neurons by using an adaptive threshold; 2) the data compression core compresses the detected AP by using an efficient Symmlet-2 discrete wavelet transform (DWT) processor for decreasing the amount of data to be transmitted by the low-power wireless link; and 3) the classification core sorts the compressed AP into separated clusters on the fly according to their wave shapes. The ND-IC encompasses several innovations: 1) the compression core decreases the complexity from O(n ²) to O(n · log(n)) compared to the previous solutions, while using two times less memory, thanks to the use of a new coefficient sorting tree; and 2) the AP classification core reuses both the compressed DWT coefficients to perform implicit dimensionality reduction, which allows for performing intensive signal processing on-chip, while increasing power and hardware efficiency. This core also reuses the signal standard deviation already computed by the AP detector core as threshold for performing automatic AP sorting. The headstage also introduces innovations by enabling a new wireless CL scheme between the neural data acquisition module and the optical stimulator. Our CL scheme uses the AP sorting and timing information produced by the ND-IC for detecting complex firing patterns within the brain. The headstage is also smaller (1.13 cm ³), lighter (3.0 g with a 40 mAh battery) and less invasive than the previous solutions, while providing a measured autonomy of 2h40, with the ND-IC. The whole system and the ND-IC are first validated in vivo in the LD thalamus of a Long-Evans rat, and then in freely-moving CL experiments involving a mouse virally expressing ChR2-mCherry in inhibitory neurons of the prelimbic cortex, and the results show that our system works well within an in vivo experimental setting with a freely moving mouse.

A Biohybrid Setup for Coupling Biological and Neuromorphic Neural Networks

Developing technologies for coupling neural activity and artificial neural components, is key for advancing neural interfaces and neuroprosthetics. We present a biohybrid experimental setting, where the activity of a biological neural network is coupled to a biomimetic hardware network. The implementation of the hardware network (denoted NeuroSoC) exhibits complex dynamics with a multiplicity of time-scales, emulating 2880 neurons and 12.7 M synapses, designed on a VLSI chip. This network is coupled to a neural network in vitro, where the activities of both the biological and the hardware networks can be recorded, processed, and integrated bidirectionally in real-time. This experimental setup enables an adjustable and well-monitored coupling, while providing access to key functional features of neural networks. We demonstrate the feasibility to functionally couple the two networks and to implement control circuits to modify the biohybrid activity. Overall, we provide an experimental model for neuromorphic-neural interfaces, hopefully to advance the capability to interface with neural activity, and with its irregularities in pathology.

A wireless and artefact-free 128-channel neuromodulation device for closed-loop stimulation and recording in non-human primates

Closed-loop neuromodulation systems aim to treat a variety of neurological conditions by delivering and adjusting therapeutic electrical stimulation in response to a patient's neural state, recorded in real time. Existing systems are limited by low channel counts, lack of algorithmic flexibility, and the distortion of recorded signals by large and persistent stimulation artefacts. Here, we describe an artefact-free wireless neuromodulation device that enables research applications requiring high-throughput data streaming, low-latency biosignal processing, and simultaneous sensing and stimulation. The device is a miniaturized neural interface capable of closed-loop recording and stimulation on 128 channels, with on-board processing to fully cancel stimulation artefacts. In addition, it can detect neural biomarkers and automatically adjust stimulation parameters in closed-loop mode. In a behaving non-human primate, the device enabled long-term recordings of local field potentials and the real-time cancellation of stimulation artefacts, as well as closed-loop stimulation to disrupt movement preparatory activity during a delayed-reach task. The neuromodulation device may help advance neuroscientific discovery and preclinical investigations of stimulation-based therapeutic interventions.

Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays

Microelectrode array (MEA) systems with up to several thousands of recording electrodes and electrical or optical stimulation capabilities are commercially available or described in the literature. By exploiting their submillisecond and micrometric temporal and spatial resolutions to record bioelectrical signals, such emerging MEA systems are increasingly used in neuroscience to study the complex dynamics of neuronal networks and brain circuits. However, they typically lack the capability of implementing real-time feedback between the detection of neuronal spiking events and stimulation, thus restricting large-scale neural interfacing to open-loop conditions. In order to exploit the potential of such large-scale recording systems and stimulation, we designed and validated a fully reconfigurable FPGA-based processing system for closed-loop multichannel control. By adopting a Xilinx Zynq-all-programmable system on chip that integrates reconfigurable logic and a dual-core ARM-based processor on the same device, the proposed platform permits low-latency preprocessing (filtering and detection) of spikes acquired simultaneously from several thousands of electrode sites. To demonstrate the proposed platform, we tested its performances through ex vivo experiments on the mice retina using a state-of-the-art planar high-density MEA that samples 4096 electrodes at 18 kHz and record light-evoked spikes from several thousands of retinal ganglion cells simultaneously. Results demonstrate that the platform is able to provide a total latency from whole-array data acquisition to stimulus generation below 2 ms. This opens the opportunity to design closed-loop experiments on neural systems and biomedical applications using emerging generations of planar or implantable large-scale MEA systems.

0.6 V, 116 nW Neural Spike Acquisition IC with Self-Biased Instrumentation Amplifier and Analog Spike Extraction

This paper presents an ultralow power 0.6 V 116 nW neural spike acquisition integrated circuit with analog spike extraction. To reduce power consumption, an ultralow power self-biased current-balanced instrumentation amplifier (IA) is proposed. The passive RC lowpass filter in the amplifier acts as both DC servo loop and self-bias circuit. The spike detector, based on an analog nonlinear energy operator consisting of a low-voltage open-loop differentiator and an open-loop gate-bulk input multiplier, is designed to emphasize the high frequency spike components nonlinearly. To reduce the spike detection error, the adjacent spike merger is also proposed. The proposed circuit achieves a low IA current consumption of 46.4 nA at 0.6 V, noise efficiency factor (NEF) of 1.81, the bandwidth from 102 Hz to 1.94 kHz, the input referred noise of 9.37 μVrms, and overall power consumption of 116 nW at 0.6 V. The proposed circuit can be used in the ultralow power spike pulses acquisition applications, including the neurofeedback systems on peripheral nerves with low neuron density.

On-Probe Neural Interface ASIC for Combined Electrical Recording and Optogenetic Stimulation

Neuromodulation technologies are progressing from pacemaking and sensory operations to full closed-loop control. In particular, optogenetics-the genetic modification of light sensitivity into neural tissue allows for simultaneous optical stimulation and electronic recording. This paper presents a neural interface application-specified integrated circuit (ASIC) for intelligent optoelectronic probes. The architecture is designed to enable simultaneous optical neural stimulation and electronic recording. It provides four low noise (2.08  μV) recording channels optimized for recording local field potentials (LFPs) (0.1-300 Hz bandwidth, 5 mV range, sampled 10-bit@4 kHz), which are more stable for chronic applications. For stimulation, it provides six independently addressable optical driver circuits, which can provide both intensity (8-bit resolution across a 1.1 mA range) and pulse-width modulation for high-radiance light emitting diodes (LEDs). The system includes a fully digital interface using a serial peripheral interface (SPI) protocol to allow for use with embedded controllers. The SPI interface is embedded within a finite state machine (FSM), which implements a command interpreter that can send out LFP data whilst receiving instructions to control LED emission. The circuit has been implemented in a commercially available 0.35  μm CMOS technology occupying a 1.95 mm 1.10 mm footprint for mounting onto the head of a silicon probe. Measured results are given for a variety of bench-top, in vitro and in vivo experiments, quantifying system performance and also demonstrating concurrent recording and stimulation within relevant experimental models.

Toward adaptive deep brain stimulation in Parkinson's disease: a review

Clinical deep brain stimulation (DBS) is now regarded as the therapeutic intervention of choice at the advanced stages of Parkinson's disease. However, some major challenges of DBS are stimulation induced side effects and limited pacemaker battery life. Side effects and shortening of pacemaker battery life are mainly as a result of continuous stimulation and poor stimulation focus. These drawbacks can be mitigated using adaptive DBS (aDBS) schemes. Side effects resulting from continuous stimulation can be reduced through adaptive control using closed-loop feedback, while those due to poor stimulation focus can be mitigated through spatial adaptation. Other advantages of aDBS include automatic, rather than manual, initial adjustment and programming, and long-term adjustments to maintain stimulation parameters with changes in patient's condition. Both result in improved efficacy. This review focuses on the major areas that are essential in driving technological advances for the various aDBS schemes. Their challenges, prospects and progress so far are analyzed. In addition, important advances and milestones in state-of-the-art aDBS schemes are highlighted – both for closed-loop adaption and spatial adaption. With perspectives and future potentials of DBS provided at the end.