A Sub- μW/Ch Analog Front-End for ∆-Neural Recording With Spike-Driven Data Compression

An Event-Based Neural Compressive Telemetry With >11× Loss-Less Data Reduction for High-Bandwidth Intracortical Brain Computer Interfaces

Intracortical brain-computer interfaces offer superior spatial and temporal resolutions, but face challenges as the increasing number of recording channels introduces high amounts of data to be transferred. This requires power-hungry data serialization and telemetry, leading to potential tissue damage risks. To address this challenge, this paper introduces an event-based neural compressive telemetry (NCT) consisting of 8 channel-rotating Δ-ADCs, an event-driven serializer supporting a proposed ternary address event representation protocol, and an event-based LVDS driver. Leveraging a high sparsity of extracellular spikes and high spatial correlation of the high-density recordings, the proposed NCT achieves a compression ratio of >11.4×, while consumes only 1 µW per channel, which is 127× more efficient than state of the art. The NCT well preserves the spike waveform fidelity, and has a low normalized RMS error <23% even with a spike amplitude down to only 31 µV.

A Modular 512-Channel Neural Signal Acquisition ASIC for High-Density 4096 Channel Electrophysiology

The complexity of information processing in the brain requires the development of technologies that can provide spatial and temporal resolution by means of dense electrode arrays paired with high-channel-count signal acquisition electronics. In this work, we present an ultra-low noise modular 512-channel neural recording circuit that is scalable to up to 4096 simultaneously recording channels. The neural readout application-specific integrated circuit (ASIC) uses a dense 8.2 mm × 6.8 mm 2D layout to enable high-channel count, creating an ultra-light 350 mg flexible module. The module can be deployed on headstages for small animals like rodents and songbirds, and it can be integrated with a variety of electrode arrays. The chip was fabricated in a TSMC 0.18 µm 1.8 V CMOS technology and dissipates a total of 125 mW. Each DC-coupled channel features a gain and bandwidth programmable analog front-end along with 14 b analog-to-digital conversion at speeds up to 30 kS/s. Additionally, each front-end includes programmable electrode plating and electrode impedance measurement capability. We present both standalone and in vivo measurements results, demonstrating the readout of spikes and field potentials that are modulated by a sensory input.

A 1024-Channel 268 nW/pixel 36×36 μm2/channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces

This paper presents a data-compressive neural recording IC for single-cell resolution high-bandwidth brain-computer interfaces. The IC features wired-OR lossy compression during digitization, thus preventing data deluge and massive data movement. By discarding unwanted baseline samples of the neural signals, the output data rate is reduced by 146× on average while allowing the reconstruction of spike samples. The recording array consists of pulse position modulation-based active digital pixels with a global single-slope analog-to-digital conversion scheme, which enables a low-power and compact pixel design with significantly simple routing and low array readout energy. Fabricated in a 28-nm CMOS process, the neural recording IC features 1024 channels (i.e., 32 × 32 array) with a pixel pitch of 36 μm that can be directly matched to a high-density microelectrode array. The pixel achieves 7.4 μVrms input-referred noise with a -3 dB bandwidth of 300-Hz to 5-kHz while consuming only 268 nW from a single 1-V supply. The IC achieves the smallest area per channel (36 × 36 μm2) and the highest energy efficiency among the state-of-the-art neural recording ICs published to date.

Power-Efficient LFP-Adaptive Dynamic Zoom-and-Track Incremental ΔΣ Front-End for Dual-Band Subcortical Recordings

We report a power-efficient analog front-end integrated circuit (IC) for multi-channel, dual-band subcortical recordings. In order to achieve high-resolution multi-channel recordings with low power consumption, we implemented an incremental ΔΣ ADC (IADC) with a dynamic zoom-and-track scheme. This scheme continuously tracks local field potential (LFP) and adaptively adjusts the input dynamic range (DR) into a zoomed sub-LFP range to resolve tiny action potentials. Thanks to the reduced DR, the oversampling rate of the IADC can be reduced by 64.3% compared to the conventional approach, leading to significant power reduction. In addition, dual-band recording can be easily attained because the scheme continuously tracks LFPs without additional on-chip hardware. A prototype four-channel front-end IC has been fabricated in 180 nm standard CMOS processes. The IADC achieved 11.3-bit ENOB at 6.8 μW, resulting in the best Walden and SNDR FoMs, 107.9 fJ/c-s and 162.1 dB, respectively, among two different comparison groups: the IADCs reported up to date in the state-of-the-art neural recording front-ends; and the recent brain recording ADCs using similar zooming or tracking techniques to this work. The intrinsic dual-band recording feature reduces the post-processing FPGA resources for subcortical signal band separation by >45.8%. The front-end IC with the zoom-and-track IADC showed an NEF of 5.9 with input-referred noise of 8.2 μVrms, sufficient for subcortical recording. The performance of the whole front-end IC was successfully validated through in vivo animal experiments.

A CMOS Microelectrode Array System With Reconfigurable Sub-Array Multiplexing Architecture Integrating 24,320 Electrodes and 380 Readout Channels

This article presents a CMOS microelectrode array (MEA) system with a reconfigurable sub-array multiplexing architecture using the time-division multiplexing (TDM) technique. The system consists of 24,320 TiN electrodes with 17.7 μm-pitch pixels and 380 column-parallel readout channels including a low-noise amplifier, a programmable gain amplifier, and a 10-b successive approximation register analog to digital converter. Readout channels are placed outside the pixel for high spatial resolution, and a flexible structure to acquire neural signals from electrodes selected by configuring in-pixel memory is realized. In this structure, a single channel can handle 8 to 32 electrodes, guaranteeing a temporal resolution from 5 kS/s to 20 kS/s for each electrode. A 128 × 190 MEA system was fabricated in a 110-nm CMOS process, and each readout channel consumes 81 μW at 1.5-V supply voltage featuring input-referred noise of 1.48 μV_rms without multiplexing and 5.4 μV_rms with multiplexing at the action-potential band (300 Hz-10 kHz).

An Implantable Neuromorphic Sensing System Featuring Near-sensor Computation and Send-on-Delta Transmission for Wireless Neural Sensing of Peripheral Nerves

This paper presents a bio-inspired event-driven neuromorphic sensing system (NSS) capable of performing on-chip feature extraction and "send-on-delta" pulse-based transmission, targeting peripheral-nerve neural recording applications. The proposed NSS employs event-based sampling which, by leveraging the sparse nature of electroneurogram (ENG) signals, achieves a data compression ratio of >125×, while maintaining a low normalized RMS error of 4% after reconstruction. The proposed NSS consists of three sub-circuits. A clockless level-crossing (LC) ADC with background offset calibration has been employed to reduce the data rate, while maintaining a high signal to quantization noise ratio. A fully synthesized spiking neural network (SNN) extracts temporal features of compound action potential signals consumes only 13 μW. An event-driven pulse-based body channel communication (Pulse-BCC) with serialized address-event representation encoding (AER) schemes minimizes transmission energy and form factor. The prototype is fabricated in 40-nm CMOS occupying a 0.32-mm² active area and consumes in total 28.2 μW and 50 μW power in feature extraction and full diagnosis mode, respectively. The presented NSS also extracts temporal features of compound action potential signals with 10-μs precision.

Low-Power Lossless Data Compression for Wireless Brain Electrophysiology

Wireless electrophysiology opens important possibilities for neuroscience, especially for recording brain activity in more natural contexts, where exploration and interaction are not restricted by the usual tethered devices. The limiting factor is transmission power and, by extension, battery life required for acquiring large amounts of neural electrophysiological data. We present a digital compression algorithm capable of reducing electrophysiological data to less than 65.5% of its original size without distorting the signals, which we tested in vivo in experimental animals. The algorithm is based on a combination of delta compression and Huffman codes with optimizations for neural signals, which allow it to run in small, low-power Field-Programmable Gate Arrays (FPGAs), requiring few hardware resources. With this algorithm, a hardware prototype was created for wireless data transmission using commercially available devices. The power required by the algorithm itself was less than 3 mW, negligible compared to the power saved by reducing the transmission bandwidth requirements. The compression algorithm and its implementation were designed to be device-agnostic. These developments can be used to create a variety of wired and wireless neural electrophysiology acquisition systems with low power and space requirements without the need for complex or expensive specialized hardware.

A 400 mV 160 nW/Ch Compact Energy Efficient ∆Σ Modulator for Multichannel Biopotential Signal Acquisition System

Analog to digitalconverter circuit design for biomedical systems with multiple recording channels presents challenges in high density and very low power consumption. Passive integrator and loop-filter based delta-sigma modulators (DSMs) have been recently reported for ultra-low-power and highly energy-efficient data converters for multi-channel biopotential acquisition. However, these modulators rely on a very high oversampling ratio (OSR) to achieve the target resolution. Higher OSR leads to higher power consumption in the modulator and the digital low-pass and decimation filter succeeding the DSM. We present a low OSR passive integrator-based DSM in this work by relying on a duty-cycled resistor (DCR). DCR enables the realization of large time constants in the already passive loop-filter, with minimal area and overhead power consumption. This leads to design of DSMs that are highly area, power and energy-efficient, suitable for multi-channel biopotential recording systems. We demonstrate a second order, duty-cycled passive integrator based CTDSM in a 65 nm CMOS technology for a 10 kHz biopotential bandwidth. Measurement results show that the fabricated design achieves an SNDR/DR of 56.36/63.1 dB while consuming only 160 nW power with an OSR of 32 and occupies an area of 0.035 mm ² with a state-of-the-art energy efficiency of 14.9 fJ/conv. In-vitro and in-vivo measurements are provided to further demonstrate the operation of the proposed DSM.

An electronic neuromorphic system for real-time detection of high frequency oscillations (HFO) in intracranial EEG

The analysis of biomedical signals for clinical studies and therapeutic applications can benefit from embedded devices that can process these signals locally and in real-time. An example is the analysis of intracranial EEG (iEEG) from epilepsy patients for the detection of High Frequency Oscillations (HFO), which are a biomarker for epileptogenic brain tissue. Mixed-signal neuromorphic circuits offer the possibility of building compact and low-power neural network processing systems that can analyze data on-line in real-time. Here we present a neuromorphic system that combines a neural recording headstage with a spiking neural network (SNN) processing core on the same die for processing iEEG, and show how it can reliably detect HFO, thereby achieving state-of-the-art accuracy, sensitivity, and specificity. This is a first feasibility study towards identifying relevant features in iEEG in real-time using mixed-signal neuromorphic computing technologies.

Analysis and Reduction of Nonlinear Distortion in AC-Coupled CMOS Neural Amplifiers with Tunable Cutoff Frequencies

Integrated CMOS neural amplifiers are key elements of modern large-scale neuroelectronic interfaces. The neural amplifiers are routinely AC-coupled to electrodes to remove the DC voltage. The large resistances required for the AC coupling circuit are usually realized using MOSFETs that are nonlinear. Specifically, designs with tunable cutoff frequency of the input high‑pass filter may suffer from excessive nonlinearity, since the gate-source voltages of the transistors forming the pseudoresistors vary following the signal being amplified. Consequently, the nonlinear distortion in such circuits may be high for signal frequencies close to the cutoff frequency of the input filter. Here we propose a simple modification of the architecture of a tunable AC-coupled amplifier, in which the bias voltages V_gs of the transistors forming the pseudoresistor are kept constant independently of the signal levels, what results in significantly improved linearity. Based on numerical simulations of the proposed circuit designed in 180 nm technology we analyze the Total Harmonic Distortion levels as a function of signal frequency and amplitude. We also investigate the impact of basic amplifier parameters—gain, cutoff frequency of the AC coupling circuit, and silicon area—on the distortion and noise performance. The post-layout simulations of the complete test ASIC show that the distortion is very significantly reduced at frequencies near the cutoff frequency, when compared to the commonly used circuits. The THD values are below 1.17% for signal frequencies 1 Hz–10 kHz and signal amplitudes up to 10 mV peak-to-peak. The preamplifier area is only 0.0046 mm² and the noise is 8.3 µV_rms in the 1 Hz–10 kHz range. To our knowledge this is the first report on a CMOS neural amplifier with systematic characterization of THD across complete range of frequencies and amplitudes of neuronal signals recorded by extracellular electrodes.

Electrophysiology Read-Out Tools for Brain-on-Chip Biotechnology

Brain-on-Chip (BoC) biotechnology is emerging as a promising tool for biomedical and pharmaceutical research applied to the neurosciences. At the convergence between lab-on-chip and cell biology, BoC couples in vitro three-dimensional brain-like systems to an engineered microfluidics platform designed to provide an in vivo-like extrinsic microenvironment with the aim of replicating tissue- or organ-level physiological functions. BoC therefore offers the advantage of an in vitro reproduction of brain structures that is more faithful to the native correlate than what is obtained with conventional cell culture techniques. As brain function ultimately results in the generation of electrical signals, electrophysiology techniques are paramount for studying brain activity in health and disease. However, as BoC is still in its infancy, the availability of combined BoC-electrophysiology platforms is still limited. Here, we summarize the available biological substrates for BoC, starting with a historical perspective. We then describe the available tools enabling BoC electrophysiology studies, detailing their fabrication process and technical features, along with their advantages and limitations. We discuss the current and future applications of BoC electrophysiology, also expanding to complementary approaches. We conclude with an evaluation of the potential translational applications and prospective technology developments.

A Real-Time Depth of Anesthesia Monitoring System Based on Deep Neural Network With Large EDO Tolerant EEG Analog Front-End

In this article, we present a real-time electroencephalogram (EEG) based depth of anesthesia (DoA) monitoring system in conjunction with a deep learning framework, AnesNET. An EEG analog front-end (AFE) that can compensate ±380-mV electrode DC offset using a coarse digital DC servo loop is implemented in the proposed system. The EEG-based MAC, EEGMAC, is introduced as a novel index to accurately predict the DoA, which is designed for applying to patients anesthetized by both volatile and intravenous agents. The proposed deep learning protocol consists of four layers of convolutional neural network and two dense layers. In addition, we optimize the complexity of the deep neural network (DNN) to operate on a microcomputer such as the Raspberry Pi 3, realizing a cost-effective small-size DoA monitoring system. Fabricated in 110-nm CMOS, the prototype AFE consumes 4.33 μW per channel and has the input-referred noise of 0.29 μVrms from 0.5 to 100 Hz with the noise efficiency factor of 2.2. The proposed DNN was evaluated with pre-recorded EEG data from 374 subjects administrated by inhalational anesthetics under surgery, achieving an average squared and absolute errors of 0.048 and 0.05, respectively. The EEGMAC with subjects anesthetized by an intravenous agent also showed a good agreement with the bispectral index value, confirming the proposed DoA index is applicable to both anesthetics. The implemented monitoring system with the Raspberry Pi 3 estimates the EEGMAC within 20 ms, which is about thousand-fold faster than the BIS estimation in literature.