Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process

An electrode-impedance-aware neurostimulator IC that achieves low-power consumption and fast charge balance

Implantable neural stimulation is becoming increasingly popular for treating neurologically impaired patients, restoring neural functions which would otherwise be lost due to diseases or injuries. The charge balance of the stimulus pulses is of paramount importance for the long-term safety of the electrode-tissue interface. This paper presents a novel neurostimulator integrated circuit in which two novel charge balancing schemes are proposed. One is based on acquiring the access resistance part (RS) of the inter-electrode impedance. Thanks to its adaptive anodic phase, the RS-based charge balance circuit does not require an additional discharge phase, achieving faster charge balance than most existing stimulator ICs. The other scheme is based on acquiring the double-layer capacitance part (CDL) of the inter-electrode impedance and the entire charge balancing process (inc. monitoring, computation and compensation) is performed in the analog domain. This is in sharp contrast to the existing electrode-impedance-aware charge balancing schemes which require ADCs and compute the net charge in the digital domain. Hence the new impedance-aware charge-balancing scheme is faster and more power friendly. The impedance-aware stimulator ASIC has been implemented using X-FAB's 180-nm CMOS process. The post-layout simulation results suggest a good charge balance is achieved as the voltage deviation from the electrode offset voltage on the electrode after the charge compensation reduces to 2.64 mV and -1.39 mV under the RS-based and CDL-based charge balancing schemes, respectively. The additional power overhead due to the proposed CDL-based charge balancer circuit is 2.46 μW at a stimulation rate of 400 Hz.

Does Charge Balancing Ensure the Safety of the Electrical Stimulation and Is It Power Efficientƒ

Safety issues are the most important concern in electrical stimulation. Equating the charge in the anodic and cathodic phases, namely charge balancing or charge equalizing, is a well-known method to avoid tissue damage and/or electrode corrosion. The electrode-tissue interface is not ideal in practice and with a charge-balanced waveform, the electrode voltage becomes more positive compared to the pre-pulse value and corrosion happens. In this paper, we show that a charge balancer ensures the safety of stimulation if the rate of the irreversible Faradaic reactions is negligible, or when the pulse width of the stimulation phases is not comparable to the time constant of the electrode-tissue interface. Furthermore, charge balancing is studied with mathematical modeling for different types of tissue models, and the results are used to show the conditions that charge balancing does not ensure the safety of the electrical stimulation, and employing charge balancing not only increases the power consumption of the electrical-stimulation systems but also increases the rate of the electrode corrosion in these conditions. The main goal of this paper is to show that a charge controller is a general solution for ensuring the safety of the electrical stimulation, with an efficient, not excessive, amount of charge for the reversal phase and should be employed instead of charge balancers in generic stimulators.

A Multimodal and Multifunctional CMOS Cellular Interfacing Array for Digital Physiology and Pathology Featuring an Ultra Dense Pixel Array and Reconfigurable Sampling Rate

The article presents a fully integrated multimodal and multifunctional CMOS biosensing/actuating array chip and system for multi-dimensional cellular/tissue characterization. The CMOS chip supports up to 1,568 simultaneous parallel readout channels across 21,952 individually addressable multimodal pixels with 13 μm × 13 μm 2-D pixel pitch along with 1,568 Pt reference electrodes. These features allow the CMOS array chip to perform multimodal physiological measurements on living cell/tissue samples with both high throughput and single-cell resolution. Each pixel supports three sensing and one actuating modalities, each reconfigurable for different functionalities, in the form of full array (FA) or fast scan (FS) voltage recording schemes, bright/dim optical detection, 2-/4-point impedance sensing (ZS), and biphasic current stimulation (BCS) with adjustable stimulation area for single-cell or tissue-level stimulation. Each multi-modal pixel contains an 8.84 μm × 11 μm Pt electrode, 4.16 μm × 7.2 μm photodiode (PD), and in-pixel circuits for PD measurements and pixel selection. The chip is fabricated in a standard 130nm BiCMOS process as a proof of concept. The on-chip electrodes are constructed by unique design and in-house post-CMOS fabrication processes, including a critical Al shorting of all pixels during fabrication and Al etching after fabrication that ensures a high-yield planar electrode array on CMOS with high biocompatibility and long-term measurement reliability. For demonstration, extensive biological testing is performed with human and mouse progenitor cells, in which multidimensional biophysiological data are acquired for comprehensive cellular characterization.

A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm2. Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode−tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.

A Multi-Channel Stimulator With High-Resolution Time-to-Current Conversion for Vagal-Cardiac Neuromodulation

This paper presents a low power integrated multi-channel stimulator for a cardiac neuroprosthesis designed to restore the parasympathetic control after heart transplantation. The proposed stimulator is based on time-to-current conversion. It replaces the conventional current mode digital-to-analog converter (DAC) that uses tens of microamps for biasing, with a novel capacitor time-based DAC (CT-DAC) offering about 10-bit current amplitude resolution with a bias current of only 250 nA. A stimulator chip was designed in a 0.18 μm CMOS high-voltage (HV) technology. It consists of 16 independent channels, each capable of delivering up to 550 μA stimulus current with a HV output stage that can be operated up to 20 V. The stimulator chip performance was evaluated using both RC equivalent load and a microelectrode array in saline solution. It is power efficient, provides high-resolution current amplitude stimulation, and has good charge balance. The design is suitable for multi-channel neural stimulation applications.