A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System

Power-to-Noise Optimization in the Design of Neural Recording Amplifier Based on Current Scaling, Source Degeneration Resistor, and Current Reuse

This article presents the design of a low-power, low-noise neural signal amplifier for neural recording. The structure reduces the current consumption of the amplifier through current scaling technology and lowers the input-referred noise of the amplifier by combining a source degeneration resistor and current reuse technologies. The amplifier was fabricated using a 0.18 μm CMOS MS RF G process. The results show the front-end amplifier exhibits a measured mid-band gain of 40 dB/46 dB and a bandwidth ranging from 0.54 Hz to 6.1 kHz; the amplifier's input-referred noise was measured to be 3.1 μVrms, consuming a current of 3.8 μA at a supply voltage of 1.8 V, with a Noise Efficiency Factor (NEF) of 2.97. The single amplifier's active silicon area is 0.082 mm2.

A Portable and a Scalable Multi-Channel Wireless Recording System for Wearable Electromyometrial Imaging

Electromyometrial imaging (EMMI) technology has emerged as one of the promising technology that can be used for non-invasive pregnancy risk stratification and for preventing complications due to pre-term birth. Current EMMI systems are bulky and require a tethered connection to desktop instrumentation, as a result, the system cannot be used in non-clinical and ambulatory settings. In this article, we propose an approach for designing a scalable, portable wireless EMMI recording system that can be used for in-home and remote monitoring. The wearable system uses a non-equilibrium differential electrode multiplexing approach to enhance signal acquisition bandwidth and to reduce the artifacts due to electrode drifts, amplifier 1/f noise, and bio-potential amplifier saturation. A combination of active shielding, a passive filter network, and a high-end instrumentation amplifier ensures sufficient input dynamic range ([Formula: see text]) such that the system can simultaneously acquire different bio-potential signals like maternal electrocardiogram (ECG) in addition to the EMMI electromyogram (EMG) signals. We show that the switching artifacts and the channel cross-talk introduced due to non-equilibrium sampling can be reduced using a compensation technique. This enables the system to be potentially scaled to a large number of channels without significantly increasing the system power dissipation. We demonstrate the feasibility of the proposed approach in a clinical setting using an 8-channel battery-powered prototype which dissipates less than 8 μW per channel for a signal bandwidth of 1 KHz.

A Wireless Headstage System Based on Neural-Recording Chip Featuring 315 nW Kickback-Reduction SAR ADC

Wireless neural-recording instruments eliminate the bulky cables in multi-channel signal transmission, while the system size should be reduced to mitigate the impact on freely-moving animals. As the battery usually dominates the system size, the neural-recording chip should be low power to minimize the battery in long-termly monitoring. In general, a neural-recording chip consists of an analog front end (AFE) and an 8 bit -10 bit analog-to-digital converter (ADC), while it's challenging to design an ADC with an 8 -10 effective number of bits (ENOB) and sub- μ W power consumption due to the kickback noise. In this work, we propose a kickback-reduction technique for a successive-approximation-register (SAR) ADC based on neural-recording chip. Fabricated in 65 nm CMOS process, the proposed technique reduce the ADC power to 315 nW, resulting in an 8-channel neural-recording chip with 249 μW in total. Measured results show that the chip achieves an ADC ENOB of 9.73 bits, as well as an AFE gain of 43.3 dB and input-referred noise (IRN) of 9.68 μV_rms in a bandwidth of 0.9 Hz -7.2 kHz. Combined with a BLE chip and a PCB antenna, the chip is implemented into a 2.6 g wireless headstage system (w/o battery), and an in-vivo demonstration is conducted on a male Sprague-Dawley rat with Parkinson's disease. The headstage system transfers the in-vivo neural signals to a commodity smartphone through BLE, and the miniature size induces little impact on freely-moving activities.

A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm2. Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode−tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.