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Tan T, Guo H, Li Y, Wang Y, Cai W, Bao W, Zhou P, Feng X. Integration of MoS 2 Memtransistor Devices and Analogue Circuits for Sensor Fusion in Autonomous Vehicle Target Localization. ACS NANO 2024; 18:13652-13661. [PMID: 38751043 DOI: 10.1021/acsnano.4c00456] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Indexed: 05/29/2024]
Abstract
In contemporary autonomous driving systems relying on sensor fusion, traditional digital processors encounter challenges associated with analogue-to-digital conversion and iterative vector-matrix operations, which are encumbered by limitations in terms of response time and energy consumption. In this study, we present an analogue Kalman filter circuit based on molybdenum disulfide (MoS2) memtransistor, designed to accelerate sensor fusion for precise localization in autonomous vehicle applications. The nonvolatile memory characteristics of the memtransistor allow for the storage of a fixed Kalman gain, which eliminates the data convergence and thus accelerates the processing speeds. Additionally, the modulation of multiple conductance states by the gate terminal enables fast adaptability to diverse autonomous driving scenarios by tuning multiple Kalman filter gains. Our proposed analogue Kalman filter circuit accurately estimates the position coordinates of target vehicles by fusing sensor data from light detection and ranging (LiDAR), millimeter-wave radar (Radar), and camera, and it successfully solves real-word problems in a signal-free crossroad intersection. Notably, our system achieves a 1000-fold improvement in energy efficiency compared to that of digital circuits. This work underscores the viability of a memtransistor for achieving fast, energy-efficient real-time sensing, and continuous signal processing in advanced sensor fusion technology.
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Affiliation(s)
- Tian Tan
- School of Mechanical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China
| | - Haoyue Guo
- School of Microelectronics, Southern University of Science and Technology, Shenzhen 518055, China
| | - Yida Li
- School of Microelectronics, Southern University of Science and Technology, Shenzhen 518055, China
| | - Yafei Wang
- School of Mechanical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China
| | - Weiwei Cai
- School of Mechanical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China
| | - Wenzhong Bao
- School of Microelectronics, Fudan University, Shanghai 200433, China
- Shaoxing Laboratory, Shaoxing 312300, China
| | - Peng Zhou
- School of Microelectronics, Fudan University, Shanghai 200433, China
| | - Xuewei Feng
- School of Mechanical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China
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2
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Wang S, Luo Y, Zuo P, Pan L, Li Y, Sun Z. In-memory analog solution of compressed sensing recovery in one step. SCIENCE ADVANCES 2023; 9:eadj2908. [PMID: 38091396 PMCID: PMC10848716 DOI: 10.1126/sciadv.adj2908] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Grants] [Track Full Text] [Download PDF] [Figures] [Subscribe] [Scholar Register] [Received: 06/17/2023] [Accepted: 11/13/2023] [Indexed: 02/12/2024]
Abstract
Modern analog computing, by gaining momentum from nonvolatile resistive memory devices, deals with matrix computations. In-memory analog computing has been demonstrated for solving some basic but ordinary matrix problems in one step. Among the more complicated matrix problems, compressed sensing (CS) is a prominent example, whose recovery algorithms feature high-order matrix operations and hardware-unfriendly nonlinear functions. In light of the local competitive algorithm (LCA), here, we present a closed-loop, continuous-time resistive memory circuit for solving CS recovery in one step. Recovery of one-dimensional (1D) sparse signal and 2D compressive images has been experimentally demonstrated, showing elapsed times around few microseconds and normalized mean squared errors of 10-2. The LCA circuit is one or two orders of magnitude faster than conventional digital approaches. It also substantially outperforms other (electronic or exotically photonic) analog CS recovery methods in terms of speed, energy, and fidelity, thus representing a highly promising technology for real-time CS applications.
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Affiliation(s)
- Shiqing Wang
- School of Integrated Circuits, Institute for Artificial Intelligence and Beijing Advanced Innovation Center for Integrated Circuits, Peking University, Beijing 100871, China
| | - Yubiao Luo
- School of Integrated Circuits, Institute for Artificial Intelligence and Beijing Advanced Innovation Center for Integrated Circuits, Peking University, Beijing 100871, China
| | - Pushen Zuo
- School of Integrated Circuits, Institute for Artificial Intelligence and Beijing Advanced Innovation Center for Integrated Circuits, Peking University, Beijing 100871, China
| | - Lunshuai Pan
- School of Integrated Circuits, Institute for Artificial Intelligence and Beijing Advanced Innovation Center for Integrated Circuits, Peking University, Beijing 100871, China
| | - Yongxiang Li
- School of Integrated Circuits, Institute for Artificial Intelligence and Beijing Advanced Innovation Center for Integrated Circuits, Peking University, Beijing 100871, China
| | - Zhong Sun
- School of Integrated Circuits, Institute for Artificial Intelligence and Beijing Advanced Innovation Center for Integrated Circuits, Peking University, Beijing 100871, China
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3
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Mikolajick T, Park MH, Begon-Lours L, Slesazeck S. From Ferroelectric Material Optimization to Neuromorphic Devices. ADVANCED MATERIALS (DEERFIELD BEACH, FLA.) 2023; 35:e2206042. [PMID: 36017895 DOI: 10.1002/adma.202206042] [Citation(s) in RCA: 21] [Impact Index Per Article: 21.0] [Reference Citation Analysis] [Abstract] [Key Words] [Grants] [Track Full Text] [Subscribe] [Scholar Register] [Received: 07/03/2022] [Revised: 08/11/2022] [Indexed: 06/15/2023]
Abstract
Due to the voltage driven switching at low voltages combined with nonvolatility of the achieved polarization state, ferroelectric materials have a unique potential for low power nonvolatile electronic devices. The competitivity of such devices is hindered by compatibility issues of well-known ferroelectrics with established semiconductor technology. The discovery of ferroelectricity in hafnium oxide changed this situation. The natural application of nonvolatile devices is as a memory cell. Nonvolatile memory devices also built the basis for other applications like in-memory or neuromorphic computing. Three different basic ferroelectric devices can be constructed: ferroelectric capacitors, ferroelectric field effect transistors and ferroelectric tunneling junctions. In this article first the material science of the ferroelectricity in hafnium oxide will be summarized with a special focus on tailoring the switching characteristics towards different applications.The current status of nonvolatile ferroelectric memories then lays the ground for looking into applications like in-memory computing. Finally, a special focus will be given to showcase how the basic building blocks of spiking neural networks, the neuron and the synapse, can be realized and how they can be combined to realize neuromorphic computing systems. A summary, comparison with other technologies like resistive switching devices and an outlook completes the paper.
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Affiliation(s)
- Thomas Mikolajick
- NaMLab gGmbH, Noethnitzer Strasse 64 a, 01187, Dresden, Germany
- Institute of Semiconductors and Microsystems, TU Dresden, 01069, Dresden, Germany
| | - Min Hyuk Park
- Department of Materials Science and Engineering and Inter-University Semiconductor Research Center, College of Engineering, Seoul National University, Gwanak-ro 1, Gwanak-gu, Seoul, 08826, Republic of Korea
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4
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Farronato M, Mannocci P, Melegari M, Ricci S, Compagnoni CM, Ielmini D. Reservoir Computing with Charge-Trap Memory Based on a MoS 2 Channel for Neuromorphic Engineering. ADVANCED MATERIALS (DEERFIELD BEACH, FLA.) 2023; 35:e2205381. [PMID: 36222391 DOI: 10.1002/adma.202205381] [Citation(s) in RCA: 5] [Impact Index Per Article: 5.0] [Reference Citation Analysis] [Abstract] [Key Words] [Grants] [Track Full Text] [Subscribe] [Scholar Register] [Received: 06/14/2022] [Revised: 09/15/2022] [Indexed: 06/16/2023]
Abstract
Novel memory devices are essential for developing low power, fast, and accurate in-memory computing and neuromorphic engineering concepts that can compete with the conventional complementary metal-oxide-semiconductor (CMOS) digital processors. 2D semiconductors provide a novel platform for advanced semiconductors with atomic thickness, low-current operation, and capability of 3D integration. This work presents a charge-trap memory (CTM) device with a MoS2 channel where memory operation arises, thanks to electron trapping/detrapping at interface states. Transistor operation, memory characteristics, and synaptic potentiation/depression for neuromorphic applications are demonstrated. The CTM device shows outstanding linearity of the potentiation by applied drain pulses of equal amplitude. Finally, pattern recognition is demonstrated by reservoir computing where the input pattern is applied as a stimulation of the MoS2 -based CTMs, while the output current after stimulation is processed by a feedforward readout network. The good accuracy, the low current operation, and the robustness to input random bit flip makes the CTM device a promising technology for future high-density neuromorphic computing concepts.
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Affiliation(s)
- Matteo Farronato
- Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano and IUNET, piazza L. da Vinci 32, Milano, 20133, Italy
| | - Piergiulio Mannocci
- Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano and IUNET, piazza L. da Vinci 32, Milano, 20133, Italy
| | - Margherita Melegari
- Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano and IUNET, piazza L. da Vinci 32, Milano, 20133, Italy
| | - Saverio Ricci
- Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano and IUNET, piazza L. da Vinci 32, Milano, 20133, Italy
| | - Christian Monzio Compagnoni
- Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano and IUNET, piazza L. da Vinci 32, Milano, 20133, Italy
| | - Daniele Ielmini
- Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano and IUNET, piazza L. da Vinci 32, Milano, 20133, Italy
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5
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Wang S, Li Y, Wang D, Zhang W, Chen X, Dong D, Wang S, Zhang X, Lin P, Gallicchio C, Xu X, Liu Q, Cheng KT, Wang Z, Shang D, Liu M. Echo state graph neural networks with analogue random resistive memory arrays. NAT MACH INTELL 2023. [DOI: 10.1038/s42256-023-00609-5] [Citation(s) in RCA: 0] [Impact Index Per Article: 0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Journal Information] [Subscribe] [Scholar Register] [Indexed: 02/15/2023]
Abstract
AbstractRecent years have witnessed a surge of interest in learning representations of graph-structured data, with applications from social networks to drug discovery. However, graph neural networks, the machine learning models for handling graph-structured data, face significant challenges when running on conventional digital hardware, including the slowdown of Moore’s law due to transistor scaling limits and the von Neumann bottleneck incurred by physically separated memory and processing units, as well as a high training cost. Here we present a hardware–software co-design to address these challenges, by designing an echo state graph neural network based on random resistive memory arrays, which are built from low-cost, nanoscale and stackable resistors for efficient in-memory computing. This approach leverages the intrinsic stochasticity of dielectric breakdown in resistive switching to implement random projections in hardware for an echo state network that effectively minimizes the training complexity thanks to its fixed and random weights. The system demonstrates state-of-the-art performance on both graph classification using the MUTAG and COLLAB datasets and node classification using the CORA dataset, achieving 2.16×, 35.42× and 40.37× improvements in energy efficiency for a projected random resistive memory-based hybrid analogue–digital system over a state-of-the-art graphics processing unit and 99.35%, 99.99% and 91.40% reductions of backward pass complexity compared with conventional graph learning. The results point to a promising direction for next-generation artificial intelligence systems for graph learning.
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6
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Lanza M, Sebastian A, Lu WD, Le Gallo M, Chang MF, Akinwande D, Puglisi FM, Alshareef HN, Liu M, Roldan JB. Memristive technologies for data storage, computation, encryption, and radio-frequency communication. Science 2022; 376:eabj9979. [PMID: 35653464 DOI: 10.1126/science.abj9979] [Citation(s) in RCA: 88] [Impact Index Per Article: 44.0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Journal Information] [Subscribe] [Scholar Register] [Indexed: 12/28/2022]
Abstract
Memristive devices, which combine a resistor with memory functions such that voltage pulses can change their resistance (and hence their memory state) in a nonvolatile manner, are beginning to be implemented in integrated circuits for memory applications. However, memristive devices could have applications in many other technologies, such as non-von Neumann in-memory computing in crossbar arrays, random number generation for data security, and radio-frequency switches for mobile communications. Progress toward the integration of memristive devices in commercial solid-state electronic circuits and other potential applications will depend on performance and reliability challenges that still need to be addressed, as described here.
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Affiliation(s)
- Mario Lanza
- Materials Science and Engineering Program, Physical Science and Engineering Division, King Abdullah University of Science and Technology (KAUST), Thuwal 23955-6900, Saudi Arabia
| | | | - Wei D Lu
- Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109, USA
| | | | - Meng-Fan Chang
- Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan.,Department of Electrical Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan
| | - Deji Akinwande
- Microelectronics Research Center, University of Texas, Austin, TX, USA
| | - Francesco M Puglisi
- Dipartimento di Ingegneria "Enzo Ferrari," Università di Modena e Reggio Emilia, 41125 Modena, Italy
| | - Husam N Alshareef
- Materials Science and Engineering Program, Physical Science and Engineering Division, King Abdullah University of Science and Technology (KAUST), Thuwal 23955-6900, Saudi Arabia
| | - Ming Liu
- Key Laboratory of Microelectronic Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
| | - Juan B Roldan
- Departamento de Electrónica y Tecnología de Computadores, Facultad de Ciencias, Universidad de Granada, 18071 Granada, Spain
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7
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Bao H, Zhou H, Li J, Pei H, Tian J, Yang L, Ren S, Tong S, Li Y, He Y, Chen J, Cai Y, Wu H, Liu Q, Wan Q, Miao X. Toward memristive in-memory computing: principles and applications. FRONTIERS OF OPTOELECTRONICS 2022; 15:23. [PMID: 36637566 PMCID: PMC9756267 DOI: 10.1007/s12200-022-00025-4] [Citation(s) in RCA: 5] [Impact Index Per Article: 2.5] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Received: 03/01/2022] [Accepted: 03/07/2022] [Indexed: 05/08/2023]
Abstract
With the rapid growth of computer science and big data, the traditional von Neumann architecture suffers the aggravating data communication costs due to the separated structure of the processing units and memories. Memristive in-memory computing paradigm is considered as a prominent candidate to address these issues, and plentiful applications have been demonstrated and verified. These applications can be broadly categorized into two major types: soft computing that can tolerant uncertain and imprecise results, and hard computing that emphasizes explicit and precise numerical results for each task, leading to different requirements on the computational accuracies and the corresponding hardware solutions. In this review, we conduct a thorough survey of the recent advances of memristive in-memory computing applications, both on the soft computing type that focuses on artificial neural networks and other machine learning algorithms, and the hard computing type that includes scientific computing and digital image processing. At the end of the review, we discuss the remaining challenges and future opportunities of memristive in-memory computing in the incoming Artificial Intelligence of Things era.
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Affiliation(s)
- Han Bao
- School of Integrated Circuits, School of Optical and Electronic Information, Wuhan National Laboratory for Optoelectronics, Optics Valley Laboratory, Huazhong University of Science and Technology, Wuhan, 430074 China
| | - Houji Zhou
- School of Integrated Circuits, School of Optical and Electronic Information, Wuhan National Laboratory for Optoelectronics, Optics Valley Laboratory, Huazhong University of Science and Technology, Wuhan, 430074 China
| | - Jiancong Li
- School of Integrated Circuits, School of Optical and Electronic Information, Wuhan National Laboratory for Optoelectronics, Optics Valley Laboratory, Huazhong University of Science and Technology, Wuhan, 430074 China
| | - Huaizhi Pei
- School of Integrated Circuits, School of Optical and Electronic Information, Wuhan National Laboratory for Optoelectronics, Optics Valley Laboratory, Huazhong University of Science and Technology, Wuhan, 430074 China
| | - Jing Tian
- School of Integrated Circuits, School of Optical and Electronic Information, Wuhan National Laboratory for Optoelectronics, Optics Valley Laboratory, Huazhong University of Science and Technology, Wuhan, 430074 China
| | - Ling Yang
- School of Integrated Circuits, School of Optical and Electronic Information, Wuhan National Laboratory for Optoelectronics, Optics Valley Laboratory, Huazhong University of Science and Technology, Wuhan, 430074 China
| | - Shengguang Ren
- School of Integrated Circuits, School of Optical and Electronic Information, Wuhan National Laboratory for Optoelectronics, Optics Valley Laboratory, Huazhong University of Science and Technology, Wuhan, 430074 China
| | - Shaoqin Tong
- School of Integrated Circuits, School of Optical and Electronic Information, Wuhan National Laboratory for Optoelectronics, Optics Valley Laboratory, Huazhong University of Science and Technology, Wuhan, 430074 China
| | - Yi Li
- School of Integrated Circuits, School of Optical and Electronic Information, Wuhan National Laboratory for Optoelectronics, Optics Valley Laboratory, Huazhong University of Science and Technology, Wuhan, 430074 China
- Hubei Yangtze Memory Laboratories, Wuhan, 430205 China
| | - Yuhui He
- School of Integrated Circuits, School of Optical and Electronic Information, Wuhan National Laboratory for Optoelectronics, Optics Valley Laboratory, Huazhong University of Science and Technology, Wuhan, 430074 China
- Hubei Yangtze Memory Laboratories, Wuhan, 430205 China
| | - Jia Chen
- AI Chip Center for Emerging Smart Systems, InnoHK Centers, Hong Kong Science Park, Hong Kong, China
| | - Yimao Cai
- School of Integrated Circuits, Peking University, Beijing, 100871 China
| | - Huaqiang Wu
- School of Integrated Circuits, Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing, 100084 China
| | - Qi Liu
- Frontier Institute of Chip and System, Fudan University, Shanghai, 200433 China
| | - Qing Wan
- School of Electronic Science and Engineering, and Collaborative Innovation Centre of Advanced Microstructures, Nanjing University, Nanjing, 210093 China
| | - Xiangshui Miao
- School of Integrated Circuits, School of Optical and Electronic Information, Wuhan National Laboratory for Optoelectronics, Optics Valley Laboratory, Huazhong University of Science and Technology, Wuhan, 430074 China
- Hubei Yangtze Memory Laboratories, Wuhan, 430205 China
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8
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Migliato Marega G, Wang Z, Paliy M, Giusi G, Strangio S, Castiglione F, Callegari C, Tripathi M, Radenovic A, Iannaccone G, Kis A. Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS 2. ACS NANO 2022; 16:3684-3694. [PMID: 35167265 PMCID: PMC8945700 DOI: 10.1021/acsnano.1c07065] [Citation(s) in RCA: 1] [Impact Index Per Article: 0.5] [Reference Citation Analysis] [Abstract] [Key Words] [Grants] [Track Full Text] [Download PDF] [Figures] [Subscribe] [Scholar Register] [Received: 08/16/2021] [Accepted: 02/07/2022] [Indexed: 06/14/2023]
Abstract
Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks. We have fabricated a flash memory array with a two-dimensional channel using wafer-scale MoS2. Simulations and experiments show that the device can be scaled down to sub-micrometer channel length without any significant impact on its memory performance and that in simulation a reasonable memory window still exists at sub-50 nm channel lengths. Each device conductance in our circuit can be tuned with a 4-bit precision by closed-loop programming. Using our physical circuit, we demonstrate seven-segment digit display classification with a 91.5% accuracy with training performed ex situ and transferred from a host. Further simulations project that at a system level, the large memory arrays can perform AlexNet classification with an upper limit of 50 000 TOpS/W, potentially outperforming neural network integrated circuits based on double-poly CMOS technology.
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Affiliation(s)
- Guilherme Migliato Marega
- Institute
of Electrical and Microengineering, École
Polytechnique Fédérale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland
- Institute
of Materials Science and Engineering, École
Polytechnique Fédérale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland
| | - Zhenyu Wang
- Institute
of Electrical and Microengineering, École
Polytechnique Fédérale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland
- Institute
of Materials Science and Engineering, École
Polytechnique Fédérale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland
| | - Maksym Paliy
- Department
of Information Engineering, University of
Pisa, I-56122 Pisa, Italy
| | - Gino Giusi
- Engineering
Department, University of Messina, I-98166 Messina, Italy
| | - Sebastiano Strangio
- Department
of Information Engineering, University of
Pisa, I-56122 Pisa, Italy
| | | | | | - Mukesh Tripathi
- Institute
of Electrical and Microengineering, École
Polytechnique Fédérale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland
- Institute
of Materials Science and Engineering, École
Polytechnique Fédérale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland
| | - Aleksandra Radenovic
- Institute
of Bioengineering, École Polytechnique
Fédérale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland
| | - Giuseppe Iannaccone
- Department
of Information Engineering, University of
Pisa, I-56122 Pisa, Italy
- Quantavis
s.r.l., Largo Padre Renzo Spadoni snc, I-56123 Pisa, Italy
| | - Andras Kis
- Institute
of Electrical and Microengineering, École
Polytechnique Fédérale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland
- Institute
of Materials Science and Engineering, École
Polytechnique Fédérale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland
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9
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Surekcigil Pesch I, Bestelink E, de Sagazan O, Mehonic A, Sporea RA. Multimodal transistors as ReLU activation functions in physical neural network classifiers. Sci Rep 2022; 12:670. [PMID: 35027631 PMCID: PMC8758690 DOI: 10.1038/s41598-021-04614-9] [Citation(s) in RCA: 3] [Impact Index Per Article: 1.5] [Reference Citation Analysis] [Abstract] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 08/12/2021] [Accepted: 12/28/2021] [Indexed: 12/03/2022] Open
Abstract
Artificial neural networks (ANNs) providing sophisticated, power-efficient classification are finding their way into thin-film electronics. Thin-film technologies require robust, layout-efficient devices with facile manufacturability. Here, we show how the multimodal transistor’s (MMT’s) transfer characteristic, with linear dependence in saturation, replicates the rectified linear unit (ReLU) activation function of convolutional ANNs (CNNs). Using MATLAB, we evaluate CNN performance using systematically distorted ReLU functions, then substitute measured and simulated MMT transfer characteristics as proxies for ReLU. High classification accuracy is maintained, despite large variations in geometrical and electrical parameters, as CNNs use the same activation functions for training and classification.
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Affiliation(s)
- Isin Surekcigil Pesch
- Advanced Technology Institute, Department of Electrical and Electronic Engineering, University of Surrey, Guildford, GU2 7XH, UK
| | - Eva Bestelink
- Advanced Technology Institute, Department of Electrical and Electronic Engineering, University of Surrey, Guildford, GU2 7XH, UK
| | | | - Adnan Mehonic
- Department of Electronic and Electrical Engineering, University College London, London, WC1E 6BT, UK
| | - Radu A Sporea
- Advanced Technology Institute, Department of Electrical and Electronic Engineering, University of Surrey, Guildford, GU2 7XH, UK.
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10
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Abstract
In-memory computing (IMC) refers to non-von Neumann architectures where data are processed in situ within the memory by taking advantage of physical laws. Among the memory devices that have been considered for IMC, the resistive switching memory (RRAM), also known as memristor, is one of the most promising technologies due to its relatively easy integration and scaling. RRAM devices have been explored for both memory and IMC applications, such as neural network accelerators and neuromorphic processors. This work presents the status and outlook on the RRAM for analog computing, where the precision of the encoded coefficients, such as the synaptic weights of a neural network, is one of the key requirements. We show the experimental study of the cycle-to-cycle variation of set and reset processes for HfO2-based RRAM, which indicate that gate-controlled pulses present the least variation in conductance. Assuming a constant variation of conductance σG, we then evaluate and compare various mapping schemes, including multilevel, binary, unary, redundant and slicing techniques. We present analytical formulas for the standard deviation of the conductance and the maximum number of bits that still satisfies a given maximum error. Finally, we discuss RRAM performance for various analog computing tasks compared to other computational memory devices. RRAM appears as one of the most promising devices in terms of scaling, accuracy and low-current operation.
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11
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Upadhyay NK, Blum T, Maksymovych P, Lavrik NV, Davila N, Katine JA, Ievlev AV, Chi M, Xia Q, Yang JJ. Engineering Tunneling Selector to Achieve High Non-linearity for 1S1R Integration. FRONTIERS IN NANOTECHNOLOGY 2021. [DOI: 10.3389/fnano.2021.656026] [Citation(s) in RCA: 6] [Impact Index Per Article: 2.0] [Reference Citation Analysis] [Abstract] [Track Full Text] [Journal Information] [Subscribe] [Scholar Register] [Indexed: 11/13/2022] Open
Abstract
Memristor devices have been extensively studied as one of the most promising technologies for next-generation non-volatile memory. However, for the memristor devices to have a real technological impact, they must be densely packed in a large crossbar array (CBA) exceeding Gigabytes in size. Devising a selector device that is CMOS compatible, 3D stackable, and has a high non-linearity (NL) and great endurance is a crucial enabling ingredient to reach this goal. Tunneling based selectors are very promising in these aspects, but the mediocre NL value limits their applications in large passive crossbar arrays. In this work, we demonstrated a trilayer tunneling selector based on the Ge/Pt/TaN1+x/Ta2O5/TaN1+x/Pd layers that could achieve a NL of 3 × 105, which is the highest NL achieved using a tunnel selector so far. The record-high tunneling NL is partially attributed to the bottom electrode's ultra-smoothness (BE) induced by a Ge/Pt layer. We further demonstrated the feasibility of 1S1R (1-selector 1-resistor) integration by vertically integrating a Pd/Ta2O5/Ru based memristor on top of the proposed selector.
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12
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Xiong F, Wang Z, Bøjesen ED, Xiong X, Zhu Z, Dong M. In Situ Resistive Switching Effect Scrutinization on Co-Designed Graphene Sensor. SMALL (WEINHEIM AN DER BERGSTRASSE, GERMANY) 2021; 17:e2007053. [PMID: 33522141 DOI: 10.1002/smll.202007053] [Citation(s) in RCA: 2] [Impact Index Per Article: 0.7] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Subscribe] [Scholar Register] [Received: 11/10/2020] [Revised: 12/23/2020] [Indexed: 06/12/2023]
Abstract
Resistive switching (RS), an electric property based on the forming and rupture of conductive filaments in metal-insulator-metal structures, has attracted intensive attention due to its potential application in next generation energy-efficient and area-efficient memory devices. In situ studies of the RS effect are urgently needed for its mechanism understanding and memristive performance improvement. Here investigations of both the RS effect as well as the gate tunable conductance quantization effect are realized by co-designing an Ag/SiO2 based memory structure on a graphene local sensor. This design enables self-monitoring of the working states of the memristor in real-time by virtue of the graphene sensor. These findings pave the way for further investigations of on-chip electronics and quantum physics.
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Affiliation(s)
- Feng Xiong
- College of Advanced Interdisciplinary Studies, National University of Defense Technology, Changsha, 410073, China
- Interdisciplinary Nanoscience Center (iNANO), Aarhus University, Aarhus C, Aarhus, DK, 8000, Denmark
| | - Zegao Wang
- Interdisciplinary Nanoscience Center (iNANO), Aarhus University, Aarhus C, Aarhus, DK, 8000, Denmark
- College of Materials Science and Engineering, Sichuan University, Chengdu, 610065, P. R. China
| | - Espen Drath Bøjesen
- Interdisciplinary Nanoscience Center (iNANO), Aarhus University, Aarhus C, Aarhus, DK, 8000, Denmark
| | - Xuya Xiong
- Interdisciplinary Nanoscience Center (iNANO), Aarhus University, Aarhus C, Aarhus, DK, 8000, Denmark
| | - Zhihong Zhu
- College of Advanced Interdisciplinary Studies, National University of Defense Technology, Changsha, 410073, China
| | - Mingdong Dong
- Interdisciplinary Nanoscience Center (iNANO), Aarhus University, Aarhus C, Aarhus, DK, 8000, Denmark
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Mikhaylov A, Pimashkin A, Pigareva Y, Gerasimova S, Gryaznov E, Shchanikov S, Zuev A, Talanov M, Lavrov I, Demin V, Erokhin V, Lobov S, Mukhina I, Kazantsev V, Wu H, Spagnolo B. Neurohybrid Memristive CMOS-Integrated Systems for Biosensors and Neuroprosthetics. Front Neurosci 2020; 14:358. [PMID: 32410943 PMCID: PMC7199501 DOI: 10.3389/fnins.2020.00358] [Citation(s) in RCA: 110] [Impact Index Per Article: 27.5] [Reference Citation Analysis] [Abstract] [Key Words] [Track Full Text] [Download PDF] [Figures] [Journal Information] [Subscribe] [Scholar Register] [Received: 10/31/2019] [Accepted: 03/24/2020] [Indexed: 11/18/2022] Open
Abstract
Here we provide a perspective concept of neurohybrid memristive chip based on the combination of living neural networks cultivated in microfluidic/microelectrode system, metal-oxide memristive devices or arrays integrated with mixed-signal CMOS layer to control the analog memristive circuits, process the decoded information, and arrange a feedback stimulation of biological culture as parts of a bidirectional neurointerface. Our main focus is on the state-of-the-art approaches for cultivation and spatial ordering of the network of dissociated hippocampal neuron cells, fabrication of a large-scale cross-bar array of memristive devices tailored using device engineering, resistive state programming, or non-linear dynamics, as well as hardware implementation of spiking neural networks (SNNs) based on the arrays of memristive devices and integrated CMOS electronics. The concept represents an example of a brain-on-chip system belonging to a more general class of memristive neurohybrid systems for a new-generation robotics, artificial intelligence, and personalized medicine, discussed in the framework of the proposed roadmap for the next decade period.
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Affiliation(s)
- Alexey Mikhaylov
- Lobachevsky State University of Nizhny Novgorod, Nizhny Novgorod, Russia
| | - Alexey Pimashkin
- Lobachevsky State University of Nizhny Novgorod, Nizhny Novgorod, Russia
| | - Yana Pigareva
- Lobachevsky State University of Nizhny Novgorod, Nizhny Novgorod, Russia
| | | | - Evgeny Gryaznov
- Lobachevsky State University of Nizhny Novgorod, Nizhny Novgorod, Russia
| | - Sergey Shchanikov
- Department of Information Technologies, Vladimir State University, Murom, Russia
| | - Anton Zuev
- Department of Information Technologies, Vladimir State University, Murom, Russia
| | - Max Talanov
- Neuroscience Laboratory, Kazan Federal University, Kazan, Russia
| | - Igor Lavrov
- Department of Neurologic Surgery, Mayo Clinic, Rochester, MN, United States
- Laboratory of Motor Neurorehabilitation, Kazan Federal University, Kazan, Russia
| | | | - Victor Erokhin
- Neuroscience Laboratory, Kazan Federal University, Kazan, Russia
- Kurchatov Institute, Moscow, Russia
- CNR-Institute of Materials for Electronics and Magnetism, Italian National Research Council, Parma, Italy
| | - Sergey Lobov
- Lobachevsky State University of Nizhny Novgorod, Nizhny Novgorod, Russia
- Center for Technologies in Robotics and Mechatronics Components, Innopolis University, Innopolis, Russia
| | - Irina Mukhina
- Lobachevsky State University of Nizhny Novgorod, Nizhny Novgorod, Russia
- Cell Technology Group, Privolzhsky Research Medical University, Nizhny Novgorod, Russia
| | - Victor Kazantsev
- Lobachevsky State University of Nizhny Novgorod, Nizhny Novgorod, Russia
- Center for Technologies in Robotics and Mechatronics Components, Innopolis University, Innopolis, Russia
| | - Huaqiang Wu
- Institute of Microelectronics, Tsinghua University, Beijing, China
| | - Bernardo Spagnolo
- Lobachevsky State University of Nizhny Novgorod, Nizhny Novgorod, Russia
- Dipartimento di Fisica e Chimica-Emilio Segrè, Group of Interdisciplinary Theoretical Physics, Università di Palermo and CNISM, Unità di Palermo, Palermo, Italy
- Istituto Nazionale di Fisica Nucleare, Sezione di Catania, Catania, Italy
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