Lossless Decompression Accelerator for Embedded Processor with GUI

Intelligent Monitoring System with Privacy Preservation Based on Edge AI

Currently, the trend of elderly people living alone is rising due to rapid aging and shifts in family structures. Accordingly, the efficient implementation and management of monitoring systems tailored for elderly people living alone have become paramount. Monitoring systems are generally implemented based on multiple sensors, and the collected data are processed on a server to provide monitoring services to users. Due to the use of multiple sensors and a reliance on servers, there are limitations to economical maintenance and a risk of highly personal information being leaked. In this paper, we propose an intelligent monitoring system with privacy preservation based on edge AI. The proposed system achieves cost competitiveness and ensures high security by blocking communication between the camera module and the server with an edge AI module. Additionally, applying edge computing technology allows for the efficient processing of data traffic. The edge AI module was designed with Verilog HDL and was implemented on a field-programmable gate array (FPGA). Through experiments conducted on 6144 frames, we achieved 95.34% accuracy. Synthesis results in a 180 nm CMOS technology indicated a gate count of 1516 K and a power consumption of 344.44 mW.

Open-Source FPGA Coprocessor for the Doppler Emulation of Moving Fluids

Embedded systems are nowadays employed in a wide range of application, and their capability to implement calculation-intensive algorithms is growing quickly and constantly. This result is obtained by the exploitation of powerful embedded processors that are often connected to coprocessors optimized for a particular application. This work presents an open-source coprocessor dedicated to the real-time generation of a synthetic signal that mimics the echoes produced by a moving fluid when investigated by ultrasounds. The coprocessor is implemented in a Field Programmable Gate Array (FPGA) device and integrated in an embedded system. The system can replace the complex and inaccurate flow-rigs employed in laboratorial tests of Doppler ultrasound systems and methods. This paper details the coprocessor and its standard interfaces, and shows how it can be integrated in the wider architecture of an embedded system. Experiments showed its capability to emulate a fluid flowing in a pipe when investigated by an echographic Doppler system.

An FPGA-Based ECU for Remote Reconfiguration in Automotive Systems

Growing interest in intelligent vehicles is leading automotive systems to include numerous electronic control units (ECUs) inside. As a result, efficient implementation and management of automotive systems is gaining importance. Flexible updating and reconfiguration of ECUs is one appropriate strategy for these goals. Software updates to the ECUs are expected to improve performance and bug handling, but there are limitations due to the fixed hardware circuit. By applying hardware-reconfigurable ECUs to the automotive system, patches that are not able to be handled with only software updates are enabled. In this paper, a remotely hardware-reconfigurable ECU for automotive systems is proposed. The proposed ECU is implemented with a field programmable gate array (FPGA) and microcontroller unit (MCU) to support in-system reconfiguration (ISR). The communication interface between the FPGA and MCU employs Zipwire communication for high speed and resilient communication. For the Zipwire communication, a Zipwire controller is designed and implemented in the FPGA. The proposed hardware-reconfigurable ECU was successfully implemented, and feasibility was demonstrated.

ASimOV: A Framework for Simulation and Optimization of an Embedded AI Accelerator

Artificial intelligence algorithms need an external computing device such as a graphics processing unit (GPU) due to computational complexity. For running artificial intelligence algorithms in an embedded device, many studies proposed light-weighted artificial intelligence algorithms and artificial intelligence accelerators. In this paper, we propose the ASimOV framework, which optimizes artificial intelligence algorithms and generates Verilog hardware description language (HDL) code for executing intelligence algorithms in field programmable gate array (FPGA). To verify ASimOV, we explore the performance space of k-NN algorithms and generate Verilog HDL code to demonstrate the k-NN accelerator in FPGA. Our contribution is to provide the artificial intelligence algorithm as an end-to-end pipeline and ensure that it is optimized to a specific dataset through simulation, and an artificial intelligence accelerator is generated in the end.