Open-Source FPGA Coprocessor for the Doppler Emulation of Moving Fluids

Embedded systems are nowadays employed in a wide range of application, and their capability to implement calculation-intensive algorithms is growing quickly and constantly. This result is obtained by the exploitation of powerful embedded processors that are often connected to coprocessors optimized for a particular application. This work presents an open-source coprocessor dedicated to the real-time generation of a synthetic signal that mimics the echoes produced by a moving fluid when investigated by ultrasounds. The coprocessor is implemented in a Field Programmable Gate Array (FPGA) device and integrated in an embedded system. The system can replace the complex and inaccurate flow-rigs employed in laboratorial tests of Doppler ultrasound systems and methods. This paper details the coprocessor and its standard interfaces, and shows how it can be integrated in the wider architecture of an embedded system. Experiments showed its capability to emulate a fluid flowing in a pipe when investigated by an echographic Doppler system.

Control and Diagnostics System Generator for Complex FPGA-Based Measurement Systems

FPGA-based data acquisition and processing systems play an important role in modern high-speed, multichannel measurement systems, especially in High-Energy and Plasma Physics. Such FPGA-based systems require an extended control and diagnostics part corresponding to the complexity of the controlled system. Managing the complex structure of registers while keeping the tight coupling between hardware and software is a tedious and potentially error-prone process. Various existing solutions aimed at helping that task do not perfectly match all specific requirements of that application area. The paper presents a new solution based on the XML system description, facilitating the automated generation of the control system’s HDL code and software components and enabling easy integration with the control software. The emphasis is put on reusability, ease of maintenance in the case of system modification, easy detection of mistakes, and the possibility of use in modern FPGAs. The presented system has been successfully used in data acquisition and preprocessing projects in high-energy physics experiments. It enables easy creation and modification of the control system definition and convenient access to the control and diagnostic blocks. The presented system is an open-source solution and may be adopted by the user for particular needs.

Blockchain-IoT Sensor (BIoTS): A Solution to IoT-Ecosystems Security Issues

Sensor devices that act in the IoT architecture perception layer are characterized by low data processing and storage capacity. These reduced capabilities make the system ubiquitous and lightweight, but considerably reduce its security. The IoT-based Food Traceability Systems (FTS), aimed at ensuring food safety and quality, serve as a motivating scenario for BIoTS development and deployment; therefore, security challenges and gaps related with data integrity are analyzed from this perspective. This paper proposes the BIoTS hardware design that contains some modules built-in VHDL (SHA-256, PoW, and SD-Memory) and other peripheral electronic devices to provide capabilities to the perception layer by implementing the blockchain architecture’s security requirements in an IoT device. The proposed hardware is implemented on FPGA Altera DE0-Nano. BIoTS can participate as a miner in the blockchain network through Smart Contracts and solve security issues related to data integrity and data traceability in an Blockchain-IoT system. Blockchain algorithms implemented in IoT hardware opens a path to IoT devices’ security and ensures participation in data validation inside a food certification process.

High throughput resource efficient reconfigurable interleaver for MIMO WLAN application

Demand for high-speed wireless broadband internet service is ever increasing. Multiple-input-multiple-output (MIMO) Wireless LAN (WLAN) is becoming a promising solution for such high-speed internet service requirements. This paper proposes a novel algorithm to efficiently model the address generation circuitry of the MIMO WLAN interleaver. The interleaver used in the MIMO WLAN transceiver has three permutation steps involving floor function whose hardware implementation is the most challenging task due to the absence of corresponding digital hardware. In this work, we propose an algorithm with a mathematical background for the address generator, eliminating the need for floor function. The algorithm is converted into digital hardware for implementation on the reconfigurable FPGA platform. Hardware structure for the complete interleaver, including the read address generator and memory module, is designed and modeled in VHDL using Xilinx Integrated Software Environment (ISE) utilizing embedded memory and DSP blocks of Spartan 6 FPGA. The functionality of the proposed algorithm is verified through exhaustive software simulation using ModelSim software. Hardware testing is carried out on Zynq 7000 FPGA using Virtual Input Output (VIO) and Integrated Logic Analyzer (ILA) core. Comparisons with few recent similar works, including the conventional Look-Up Table (LUT) based technique, show the superiority of our proposed design in terms of maximum improvement in operating frequency by 196.83%, maximum reduction in power consumption by 74.27%, and reduction of memory occupancy by 88.9%. In the case of throughput, our design can deliver 8.35 times higher compared to IEEE 802.11n requirement.

FPGA implementation of neuro-fuzzy system with improved PSO learning

This paper presents the first hardware implementation of neuro-fuzzy system (NFS) with its metaheuristic learning ability on field programmable gate array (FPGA). Metaheuristic learning of NFS for all of its parameters is accomplished by using the improved particle swarm optimization (iPSO). As a second novelty, a new functional approach, which does not require any memory and multiplier usage, is proposed for the Gaussian membership functions of NFS. NFS and its learning using iPSO are implemented on Xilinx Virtex5 xc5vlx110-3ff1153 and efficiency of the proposed implementation tested on two dynamic system identification problems and licence plate detection problem as a practical application. Results indicate that proposed NFS implementation and membership function approximation is as effective as the other approaches available in the literature but requires less hardware resources.

De novo characterization of transcriptome and gene expression dynamics in epidermis during the larval-pupal metamorphosis of common cutworm

Larval cuticle is degraded and replaced by the pupal counterpart during larval-pupal metamorphosis in the holometabolous insects. In addition to the extrinsic transformation, the epidermis goes through significant changes at molecular levels. To elucidate the intrinsic mechanism of epidermal metamorphosis, the dynamics of chitin content in the cuticle was examined in an important agricultural lepidopteran, the common cutworm, and the transcriptome was analyzed using Illumina sequencing technology. Gene expression profiles during the metamorphosis were further studied by both the digital gene expression (DGE) system and real-time quantitative PCR. The results showed that the chitin content decreased in prepupae and then increased in pupae. A total of 58 million sequencing reads were obtained and assembled into 70,346 unigenes. Over 9000 unigenes were identified to express differentially during the transformation process. As compared with the 6th instar feeding larvae, the most significant changes took place in the proteasome and metabolic pathways in prepupae and pupae, respectively. The cytochrome P450s, VHDLs, chitinase, serine protease and genes involved in sex pheromone biosynthesis changed their mRNA levels remarkably. Three chitinolytic enzymes (chitinase, β-N-acetylglucosaminidase and chitin deacetylase) showed distinct mRNA expression patterns, the former two enzymes revealed the highest expression in prepupae, however the latter one showed its climax mRNA level in pupae. The gene expression patterns suggest that chitinase and β-N-acetylglucosaminidase may be responsible for the degradation of larval cuticles, whereas chitin deacetylase may help to degrade the pupal counterparts. Gene expression dynamics also implied that the chitin of pupal cuticle might be formed by recycling of the degraded chitin of larval cuticle rather than through de novo synthesis. The 20E-induced nuclear receptors seem to be important factors regulating chitin metabolic enzymes during the cuticle remodeling. Our data provide a comprehensive resource for exploring the molecular mechanism of epidermal metamorphosis in insects.

Comparison between Frame-Constrained Fix-Pixel-Value and Frame-Free Spiking-Dynamic-Pixel ConvNets for Visual Processing

Most scene segmentation and categorization architectures for the extraction of features in images and patches make exhaustive use of 2D convolution operations for template matching, template search, and denoising. Convolutional Neural Networks (ConvNets) are one example of such architectures that can implement general-purpose bio-inspired vision systems. In standard digital computers 2D convolutions are usually expensive in terms of resource consumption and impose severe limitations for efficient real-time applications. Nevertheless, neuro-cortex inspired solutions, like dedicated Frame-Based or Frame-Free Spiking ConvNet Convolution Processors, are advancing real-time visual processing. These two approaches share the neural inspiration, but each of them solves the problem in different ways. Frame-Based ConvNets process frame by frame video information in a very robust and fast way that requires to use and share the available hardware resources (such as: multipliers, adders). Hardware resources are fixed- and time-multiplexed by fetching data in and out. Thus memory bandwidth and size is important for good performance. On the other hand, spike-based convolution processors are a frame-free alternative that is able to perform convolution of a spike-based source of visual information with very low latency, which makes ideal for very high-speed applications. However, hardware resources need to be available all the time and cannot be time-multiplexed. Thus, hardware should be modular, reconfigurable, and expansible. Hardware implementations in both VLSI custom integrated circuits (digital and analog) and FPGA have been already used to demonstrate the performance of these systems. In this paper we present a comparison study of these two neuro-inspired solutions. A brief description of both systems is presented and also discussions about their differences, pros and cons.