Acquisition of Neural Action Potentials Using Rapid Multiplexing Directly at the Electrodes

Brain Feature Extraction With an Artifact-Tolerant Multiplexed Time-Encoding Neural Frontend for True Real-Time Closed-Loop Neuromodulation

Closed-loop neuromodulation is emerging as a more effective and targeted solution for the treatment of neurological symptoms compared to traditional open-loop stimulation. The majority of the present designs lack the ability to continuously record brain activity during electrical stimulation; hence they cannot fully monitor the treatment's effectiveness. This is due to the large stimulation artifacts that can saturate the sensitive readout circuits. To overcome this challenge, this work presents a rapid-artifact-recovery time-multiplexed neural readout frontend in combination with backend linear interpolation to reconstruct the artifact-corrupted local field potentials' (LFP) features. Our hybrid technique is an alternative approach to avoid power-hungry large-dynamic-range readout architectures or large and complex artifact template subtraction circuits. We discuss the design and measurements of a prototype implementation of the proposed readout frontend in 180-nm CMOS. It combines time multiplexing and time-domain conversion in a novel 13-bit incremental ADC, requiring only 0.0018 mm2/channel of readout area despite the large 180-nm CMOS process used, while consuming only 4.51 μW/channel. This is the smallest reported area for stimulation-voltage-compatible technologies (i.e. ≥ 65 nm). The frontend also yields a best-in-class peak total harmonic distortion of -72.6 dB @2.5-mVpp input, thanks to its implicit DAC mismatch-error shaping property. We employ the chip to measure brain LFP signals corrupted with artifacts, then perform linear interpolation and feature extraction on the measured signals and evaluate the reconstruction quality, using a set of sixteen commonly used features and three stimulation scenarios. The results show relative accuracies above 95% with respect to the situation without artifacts. This work is an ideal candidate for integration in high-channel-count true closed-loop neuromodulation systems.

Stable, chronic in-vivo recordings from a fully wireless subdural-contained 65,536-electrode brain-computer interface device

Minimally invasive, high-bandwidth brain-computer-interface (BCI) devices can revolutionize human applications. With orders-of-magnitude improvements in volumetric efficiency over other BCI technologies, we developed a 50-μm-thick, mechanically flexible micro-electrocorticography (μECoG) BCI, integrating 256×256 electrodes, signal processing, data telemetry, and wireless powering on a single complementary metal-oxide-semiconductor (CMOS) substrate containing 65,536 recording and 16,384 stimulation channels, from which we can simultaneously record up to 1024 channels at a given time. Fully implanted below the dura, our chip is wirelessly powered, communicating bi-directionally with an external relay station outside the body. We demonstrated chronic, reliable recordings for up to two weeks in pigs and up to two months in behaving non-human primates from somatosensory, motor, and visual cortices, decoding brain signals at high spatiotemporal resolution.

Multiplexed Surface Electrode Arrays Based on Metal Oxide Thin-Film Electronics for High-Resolution Cortical Mapping

Electrode grids are used in neuroscience research and clinical practice to record electrical activity from the surface of the brain. However, existing passive electrocorticography (ECoG) technologies are unable to offer both high spatial resolution and wide cortical coverage, while ensuring a compact acquisition system. The electrode count and density are restricted by the fact that each electrode must be individually wired. This work presents an active micro-electrocorticography (µECoG) implant that tackles this limitation by incorporating metal oxide thin-film transistors (TFTs) into a flexible electrode array, allowing to address multiple electrodes through a single shared readout line. By combining the array with an incremental-ΔΣ readout integrated circuit (ROIC), the system is capable of recording from up to 256 electrodes virtually simultaneously, thanks to the implemented 16:1 time-division multiplexing scheme, offering lower noise levels than existing active µECoG arrays. In vivo validation is demonstrated acutely in mice by recording spontaneous activity and somatosensory evoked potentials over a cortical surface of ≈8×8 mm2 . The proposed neural interface overcomes the wiring bottleneck limiting ECoG arrays, holding promise as a powerful tool for improved mapping of the cerebral cortex and as an enabling technology for future brain-machine interfaces.

UWB-Modulated Microwave Imaging for Human Brain Functional Monitoring

Morphological microwave imaging has shown interesting results on reconstructing biological objects inside the human body, and these parameters represent their actual biological condition, but not their biological activity. In this paper, we propose a novel microwave technique to locate the low-frequency (f≃1 kHz) -modulated signals produced by a microtag mimicking an action potential and proved it in a cylindrical phantom of the brain region. A set of two combined UWB microwave applicators, operating in the 0.5 to 2.5 GHz frequency band and producing a nsec interrogation pulse, is able to focus its radiated field into a small region of the brain containing the microtag with a modulated photodiode. The illuminating UWB microwave field was first modulated by the low-frequency (f≃1 kHz) electrical signal produced by the photodiode, inducing modulated microwave currents into the microtag that reradiating back towards the focusing applicators. At the receiving end, the low-frequency (f≃1 kHz) -modulated signal was first extracted from the full set of the backscattered signals, then focused into the region of interest and spatially represented in the corresponding region of the brain, resulting in a spatial resolution of the images in the order of 10 mm.

An AC-Coupled 1st-order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition

The current demand for high-channel-count neural-recording interfaces calls for more area- and power-efficient readout architectures that do not compromise other electrical performances. In this paper, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range and electrode DC offset cancellation. An AC-coupled 1st-order digitally-intensive Δ - Δ Σ architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits and a digital control, has been fabricated in 22-nm FDSOI CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm2, a total power per channel of 12.57 μ W , and an input-referred noise of 7.7 ± 0.4 μ V rms in the AP band and 11.9 ± 1.1 μ V rms in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated in vivo, demonstrating its capability to successfully record full-band neural signals.

A CMOS Microelectrode Array System With Reconfigurable Sub-Array Multiplexing Architecture Integrating 24,320 Electrodes and 380 Readout Channels

This article presents a CMOS microelectrode array (MEA) system with a reconfigurable sub-array multiplexing architecture using the time-division multiplexing (TDM) technique. The system consists of 24,320 TiN electrodes with 17.7 μm-pitch pixels and 380 column-parallel readout channels including a low-noise amplifier, a programmable gain amplifier, and a 10-b successive approximation register analog to digital converter. Readout channels are placed outside the pixel for high spatial resolution, and a flexible structure to acquire neural signals from electrodes selected by configuring in-pixel memory is realized. In this structure, a single channel can handle 8 to 32 electrodes, guaranteeing a temporal resolution from 5 kS/s to 20 kS/s for each electrode. A 128 × 190 MEA system was fabricated in a 110-nm CMOS process, and each readout channel consumes 81 μW at 1.5-V supply voltage featuring input-referred noise of 1.48 μV_rms without multiplexing and 5.4 μV_rms with multiplexing at the action-potential band (300 Hz-10 kHz).

Noise Power Minimization in CMOS Brain-Chip Interfaces

This paper presents specific noise minimization strategies to be adopted in silicon–cell interfaces. For this objective, a complete and general model for the analog processing of the signal coming from cell–silicon junctions is presented. This model will then be described at the level of the single stages and of the fundamental parameters that characterize them (bandwidth, gain and noise). Thanks to a few design equations, it will therefore be possible to simulate the behavior of a time-division multiplexed acquisition channel, including the most relevant parameters for signal processing, such as amplification (or power of the analog signal) and noise. This model has the undoubted advantage of being particularly simple to simulate and implement, while maintaining high accuracy in estimating the signal quality (i.e., the signal-to-noise ratio, SNR). Thanks to the simulation results of the model, it will be possible to set an optimal operating point for the front-end to minimize the artifacts introduced by the time-division multiplexing (TDM) scheme and to maximize the SNR at the a-to-d converter input. The proposed results provide an SNR of 12 dB at 10 µV_RMS of noise power and 50 µV_RMS of signal power (both evaluated at input of the analog front-end, AFE). This is particularly relevant for cell–silicon junctions because it demonstrates that it is possible to detect weak extracellular events (of the order of few µV_RMS) without necessarily increasing the total amplification of the front-end (and, therefore, as a first approximation, the dissipated electrical power), while adopting a specific gain distribution through the acquisition chain.

A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System

This paper presents a low-power, low-noise microsystem for the recording of neural local field potentials or intracranial electroencephalographic signals. It features 32 time-multiplexed channels at the electrode interface and offers the possibility to spatially delta encode data to take advantage of the large correlation of signals captured from nearby channels. The circuit also implements a mixed-signal voltage-triggered auto-ranging algorithm which allows to attenuate large interferers in digital domain while preserving neural information. This effectively increases the system dynamic range and avoids the onset of saturation. A prototype, fabricated in a standard 180 nm CMOS process, has been experimentally verified in-vitro with cellular cultures of primary cortical neurons from mice. The system shows an integrated input-referred noise in the 0.5-200 Hz band of 1.4 μV_rms for a spot noise of about 85 nV /√{Hz}. The system draws 1.5 μW per channel from 1.2 V supply and obtains 71 dB + 26 dB dynamic range when the artifact-aware auto-ranging mechanism is enabled, without penalising other critical specifications such as crosstalk between channels or common-mode and power supply rejection ratios.

Closed-Loop Neural Prostheses With On-Chip Intelligence: A Review and a Low-Latency Machine Learning Model for Brain State Detection

The application of closed-loop approaches in systems neuroscience and therapeutic stimulation holds great promise for revolutionizing our understanding of the brain and for developing novel neuromodulation therapies to restore lost functions. Neural prostheses capable of multi-channel neural recording, on-site signal processing, rapid symptom detection, and closed-loop stimulation are critical to enabling such novel treatments. However, the existing closed-loop neuromodulation devices are too simplistic and lack sufficient on-chip processing and intelligence. In this paper, we first discuss both commercial and investigational closed-loop neuromodulation devices for brain disorders. Next, we review state-of-the-art neural prostheses with on-chip machine learning, focusing on application-specific integrated circuits (ASIC). System requirements, performance and hardware comparisons, design trade-offs, and hardware optimization techniques are discussed. To facilitate a fair comparison and guide design choices among various on-chip classifiers, we propose a new energy-area (E-A) efficiency figure of merit that evaluates hardware efficiency and multi-channel scalability. Finally, we present several techniques to improve the key design metrics of tree-based on-chip classifiers, both in the context of ensemble methods and oblique structures. A novel Depth-Variant Tree Ensemble (DVTE) is proposed to reduce processing latency (e.g., by 2.5× on seizure detection task). We further develop a cost-aware learning approach to jointly optimize the power and latency metrics. We show that algorithm-hardware co-design enables the energy- and memory-optimized design of tree-based models, while preserving a high accuracy and low latency. Furthermore, we show that our proposed tree-based models feature a highly interpretable decision process that is essential for safety-critical applications such as closed-loop stimulation.

Recording Strategies for High Channel Count, Densely Spaced Microelectrode Arrays

Neuroscience research into how complex brain functions are implemented at an extra-cellular level requires in vivo neural recording interfaces, including microelectrodes and read-out circuitry, with increased observability and spatial resolution. The trend in neural recording interfaces toward employing high-channel-count probes or 2D microelectrodes arrays with densely spaced recording sites for recording large neuronal populations makes it harder to save on resources. The low-noise, low-power requirement specifications of the analog front-end usually requires large silicon occupation, making the problem even more challenging. One common approach to alleviating this consumption area burden relies on time-division multiplexing techniques in which read-out electronics are shared, either partially or totally, between channels while preserving the spatial and temporal resolution of the recordings. In this approach, shared elements have to operate over a shorter time slot per channel and active area is thus traded off against larger operating frequencies and signal bandwidths. As a result, power consumption is only mildly affected, although other performance metrics such as in-band noise or crosstalk may be degraded, particularly if the whole read-out circuit is multiplexed at the analog front-end input. In this article, we review the different implementation alternatives reported for time-division multiplexing neural recording systems, analyze their advantages and drawbacks, and suggest strategies for improving performance.

Charge-Redistribution Based Quadratic Operators for Neural Feature Extraction

This paper presents a SAR converter based mixed-signal multiplier for the feature extraction of neural signals using quadratic operators. After a thorough analysis of design principles and circuit-level aspects, the proposed architecture is explored for the implementation of two quadratic operators often used for the characterization of neural activity, the moving average energy (MAE) operator and the nonlinear energy operator (NEO). Programmable chips for both operators have been implemented in a HV-180 nm CMOS process. Experimental results confirm their suitability for energy computation and action potential detection and the accomplished area×power performance is compared to prior art. The MAE and NEO prototypes, at a sampling rate of 30kS/s, consume 116 nW and 178 nW, respectively, and digitize both the input neural signal and the operator outcome, with no need for digital multipliers.

A 0.0023 mm 2/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression

This article demonstrates a scalable, time-division multiplexed biopotential recording front-end capable of real-time differential- and common-mode artifact suppression. A delta-encoded recording architecture exploits the power spectral density (PSD) characteristics of Electrocorticography (ECoG) recordings, combining an 8-bit ADC, and an 8-bit DAC to achieve 14 bits of dynamic range. The flexibility of the digital feedback architecture is leveraged to time-division multiplex 64 differential input channels onto a shared mixed-signal front-end, reducing channel area by 2x compared to the state-of-the-art. The feedback DAC used for delta-encoding also serves to cancel differential artifacts with an off-chip adaptive loop. Analysis of this architecture and measured silicon performance of a 65 nm CMOS test-chip implementation, both on the bench and in-vivo, are included with this paper.

A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording

Neural interfaces of the future will be used to help restore lost sensory, motor, and other capabilities. However, realizing this futuristic promise requires a major leap forward in how electronic devices interface with the nervous system. Next generation neural interfaces must support parallel recording from tens of thousands of electrodes within the form factor and power budget of a fully implanted device, posing a number of significant engineering challenges. In this paper, we exploit sparsity and diversity of neural signals to achieve simultaneous data compression and channel multiplexing for neural recordings. The architecture uses wired-OR interactions within an array of single-slope A/D converters to obtain massively parallel digitization of neural action potentials. The achieved compression is lossy but effective at retaining the critical samples belonging to action potentials, enabling efficient spike sorting and cell type identification. Simulation results of the architecture using data obtained from primate retina ex-vivo with a 512-channel electrode array show average compression rates up to  ∼ 40× while missing less than 5% of cells. In principle, the techniques presented here could be used to design interfaces to other parts of the nervous system.

A Compact Quad-Shank CMOS Neural Probe With 5,120 Addressable Recording Sites and 384 Fully Differential Parallel Channels

Large-scale in vivo electrophysiology requires tools that enable simultaneous recording of multiple brain regions at single-neuron level. This calls for the design of more compact neural probes that offer even larger arrays of addressable sites and high channel counts. With this aim, we present in this paper a quad-shank approach to integrate as many as 5,120 sites on a single probe. Compact fully-differential recording channels were designed using a single-gain-stage neural amplifier with a 14-bit ADC, achieving a mean input-referred noise of 7.44 μV_rms in the action-potential band and 7.65 μV_rms in the local-field-potential band, a mean total harmonic distortion of 0.17% at 1 kHz and a mean input-referred offset of 169 μV. The probe base incorporates 384 channels with on-chip power management, reference-voltage generation and digital control, thus achieving the highest level of integration in a neural probe and excellent channel-to-channel uniformity. Therefore, no calibration or external circuitry are required to achieve the above-mentioned performance. With a total area of 2.2 × 8.67 mm² and a power consumption of 36.5 mW, the presented probe enables full-system miniaturization for acute or chronic use in small rodents.

Verification of a Rapidly Multiplexed Circuit for Scalable Action Potential Recording

This report presents characterizations of in vivo neural recordings performed with a CMOS multichannel neural recording chip that uses rapid multiplexing directly at the electrodes, without any pre-amplification or buffering. Neural recordings were taken from a 16-channel microwire array implanted in rodent cortex, with comparison to a gold-standard commercial bench-top recording system. We were able to record well-isolated threshold crossings from 10 multiplexed electrodes and typical local field potential waveforms from 16, with strong agreement with the standard system (average SNR = 2.59 and 3.07 respectively). For 10 electrodes, the circuit achieves an effective area per channel of 0.0077 mm², which is >5x smaller than typical multichannel chips. Extensive characterizations of noise and signal quality are presented and compared to fundamental theory, as well as results from in vivo and in vitro experiments. By demonstrating the validation of rapid multiplexing directly at the electrodes, this report confirms it as a promising approach for reducing circuit area in massively-multichannel neural recording systems, which is crucial for scaling recording site density and achieving large-scale sensing of brain activity with high spatiotemporal resolution.

Editorial for the Special Issue on Neural Electrodes: Design and Applications

Neural electrodes enable the recording and stimulation of bioelectrical activity from the nervous system [...].